Investigation of the potential of organic circuits for RFID tags Qintao Zhang and Sha Li.

Slides:



Advertisements
Similar presentations
Chapter 10 Digital CMOS Logic Circuits
Advertisements

Alessandro Marras, Ilaria De Munari, Davide Vescovi, Paolo Ciampolini Università di Parma Performance Evaluation of Ultrathin gate oxide CMOS Circuits.
Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)
ECE 424 – Introduction to VLSI
Physical structure of a n-channel device:
COMP541 Transistors and all that… a brief overview
Slides based on Kewal Saluja
Metal Oxide Semiconductor Field Effect Transistors
Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.
MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM.
CMOS Family.
Introduction to Digital Systems By Dr. John Abraham UT-Panam.
Chun-Chieh Lu Carbon-based devices on flexible substrate 1.
From analog to digital circuits A phenomenological overview Bogdan Roman.
Digital Integrated Circuits© Prentice Hall 1995 Devices The MOS Transistor.
Advance Nano Device Lab. Fundamentals of Modern VLSI Devices 2 nd Edition Yuan Taur and Tak H.Ning 0 Ch5. CMOS Performance Factors.
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004.
VLSI Design CMOS Transistor Theory. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V.
Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.
EE42/100, Spring 2006Week 14a, Prof. White1 Week 14a Propagation delay of logic gates CMOS (complementary MOS) logic gates Pull-down and pull-up The basic.
11/5/2004EE 42 fall 2004 lecture 281 Lecture #28 PMOS LAST TIME: NMOS Electrical Model – NMOS physical structure: W and L and d ox, TODAY: PMOS –Physical.
Lecture 21 Today we will Revisit the CMOS inverter, concentrating on logic 0 and logic 1 inputs Come up with an easy model for MOS transistors involved.
Lecture #24 Gates to circuits
Integrated Circuits CSE 495/595 Review Supplement.
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007.
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory
Physical States for Bits. Black Box Representations.
1 NE479 Winter 2010 R. Denomme/R.Swaminathan 1 Organic RFIDs Ryan Denomme Rajesh Kumar NE 479 Project Presentation Winter 2010.
Characterization of a CMOS cell library for low-voltage operation
Major Numeric Data Types Unsigned Integers Signed Integers Alphanumeric Data – ASCII & UNICODE Floating Point Numbers.
Design and Implementation of VLSI Systems (EN1600) lecture02 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.
CS 140L Lecture 1 Professor CK Cheng 3/31/02. CMOS Logic (3.2 – 3.6) Complementary Metal-Oxide Semiconductor.
8/23-25/05ELEC / Lecture 21 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Chap. 5 Field-effect transistors (FET) Importance for LSI/VLSI –Low fabrication cost –Small size –Low power consumption Applications –Microprocessors –Memories.
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 5 Dr. Shi Dept. of Electrical and Computer Engineering.
S. RossEECS 40 Spring 2003 Lecture 24 Today we will Review charging of output capacitance (origin of gate delay) Calculate output capacitance Discuss fan-out.
MOS Capacitors ECE Some Classes of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor ▫ MOSFET, which will be the type that.
Digital Integrated Circuits© Prentice Hall 1995 Inverter THE INVERTERS.
ECE 331 – Digital System Design Transistor Technologies, and Realizing Logic Gates using CMOS Circuits (Lecture #23)
EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style Sumeer Goel, Ashok Kumar, and Magdy A. Bayoumi.
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n Circuit design for FPGAs: –Logic elements. –Interconnect.
2. Transistors and Layout Fabrication techniques Transistors and wires Design rule for layout Basic concepts and tools for Layout.
THE INVERTERS. DIGITAL GATES Fundamental Parameters l Functionality l Reliability, Robustness l Area l Performance »Speed (delay) »Power Consumption »Energy.
16-1 McGraw-Hill Copyright © 2001 by the McGraw-Hill Companies, Inc. All rights reserved. Chapter Sixteen MOSFET Digital Circuits.
Ratioed Circuits Ratioed circuits use weak pull-up and stronger pull-down networks. The input capacitance is reduced and hence logical effort. Correct.
Subsystem Design 2 EE213 VLSI Design This section contains some notes on logic implementation and more complex gates etc. Full details are in Pucknell.
ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Static CMOS Logic ECE442: Digital Electronics.
An Oscillator Design Based on Bi-CMOS Differential Amplifier Using Standard SiGe Process Cher-Shiung Tsai, Ming-Hsin Lin, Ping-Feng Wu, Chang-Yu Li, Yu-Nan.
Supply Voltage Biasing Andy Whetzel and Elena Weinberg University of Virginia.
HOMEWORK 4-1 Compute the low and high noise margins using the following transfer curve of a Pseudo-pMOS inverter.
UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY
Notes on Transistor Sizing for equal pullup/pulldown We assume that electron mobility to hole mobility ratio is 2 in this class. This means that a minimum.
EE141 © Digital Integrated Circuits 2nd Devices 1 Goal of this lecture  Present understanding of device operation  nMOS/pMOS as switches  How to design.
CMOS Fabrication nMOS pMOS.
Complementary MOS inverter “CMOS” inverter n channel enhancement mode (V TN > 0) in series with a p channel enhancement mode (V TP < 0) 0 < V in < V.
Static CMOS Logic Seating chart updates
Chapter 6 Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. High-Speed CMOS Logic Design.
MOS Capacitors UoG-UESTC Some Classes of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor ▫ MOSFET, which will be the.
CHAPTER 6: MOSFET & RELATED DEVICES CHAPTER 6: MOSFET & RELATED DEVICES Part 2.
Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: CMOS circuits,
CMOS Logic Gates. NMOS transistor acts as a switch 2 When gate voltage is 0 V No channel is formed current does not flow easily “open switch” When gate.
Introduction to CMOS Transistor and Transistor Fundamental
EE415 VLSI Design. Read 4.1, 4.2 COMBINATIONAL LOGIC.
Introduction to CMOS VLSI Design CMOS Transistor Theory
Vladimir Gromov, NIKHEF, Amsterdam. GOSSIPO-3 Working Group February 03, Local Oscillator in the GOSSIPO-3 readout chip.
THE CMOS INVERTER.
Downsizing Semiconductor Device (MOSFET)
Downsizing Semiconductor Device (MOSFET)
Presentation transcript:

Investigation of the potential of organic circuits for RFID tags Qintao Zhang and Sha Li

Matthias Handy RFID-Workshop, 30.9./ , Berlin

Organic transistors Organic tags are the only way of under-1-cent RFID tags Cgd0Cgs0

Good and Bad things No standard structures, L=5mm~10nm, W=several 100um~10mm, large overlap capacitance No standard semiconductor materials, Pentacene, P3HT, CuPc No Standard gate dielectric, K=2 to 16 No control of parameters, lots of different Vt reported fabrication limitation: Can’t shrink devices, typical number L=2µm, W=50µm for inkjet printing Flexible fabrication: soluble materials can be printed on all kinds of material Transparent, important for display, may get e-paper, e-poster Good things: Bad things:

AIM-spice Model Good enough Mobility 3cm 2 /V S Supply voltage 40V Channel Length 2µm2µm Contact resistance 7E5 ohm Channel width 50µm

Inverter Complementary Static inverter Organic Inverter CMOS Inverter

Inverter Pseudo-PMOS Depletion Load PMOS

Ring Oscillator Using Complementary inverter Wp/Wn=1/1, Vdd=40V, Freq=394.42KHz,P=490uW Wp/Wn=1/15, Vdd=40V, Freq=70.741KHz, P=81uW Wp/Wn=1/1, Vdd=14.3V, Freq=125.36KHz, P=15.7uW

Ring Oscillator Pseudo-PMOS COMPLEMENTARY (15/1) PSEUDODEPLETION Tp (us)14.136/ Frequency (KHz)70.741/ Power (uW)81.027/ Depletion Load PMOS

NAND and NOR Complementary NAND Complementary NOR

NAND and NOR COMPLEMENTARY NAND COMPLEMENTARY NORRATIO NAND DCVSL Thl (us)2.63/ / Tlh(us)2.01/ / Frequency (KHz)380/ / Power (uW)195/ / DCVSL

Memory Mainly use P-type transistor in the ROM to improve the performance. OR ROM NOR ROM OR ROMNOR ROM Tp (ns) Frequency (MHz) Power (uW)250256

Decoder OR ROMDECODERDECODER+ROM Tp (us) Frequency (KHz) Power (uW) Decoder + OR ROM Decoder W=min Decoder Wp/Wn=2/15

Conclusion Using current organic transistor technology, it is possible to run the RFID at 125KHz. Due to the big size of the device, the power consumption is much bigger than the regular CMOS circuit. This severely reduces the working distance of the organic RFID.