Comparison of LFSR and CA for BIST

Slides:



Advertisements
Similar presentations
Introduction to DFT Alexander Gnusin.
Advertisements

Digital Integrated Circuits© Prentice Hall 1995 Design Methodologies Design for Test.
MEMORY BIST by: Saeid Hashemi Mehrdad Falakparvaz
V. Vaithianathan, AP/ECE
Design for Testability (DfT)
Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n Functional test n Diagnostic test  Fault dictionary  Diagnostic.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 261 Lecture 26 Logic BIST Architectures n Motivation n Built-in Logic Block Observer (BILBO) n Test.
1 Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults Chidambaram Alagappan Vishwani D. Agrawal Department of Electrical and Computer.
5/13/2015 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Built-in Self-test.
1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
Scalable Test Pattern Generator Design Method for BIST Petr Fišer, Hana Kubátová Czech Technical University in Prague Faculty of Electrical Engineering.
Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt1 Lecture 21alt BIST -- Built-In Self-Test (Alternative to Lectures 25, 26 and 27) n Definition.
Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, AL 36849
Testability Virendra Singh Indian Institute of Science Bangalore
11/17/05ELEC / Lecture 201 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Linearization of Stream Ciphers in Terms of Cellular Automata Amparo Fúster-Sabater Institute of Applied Physics (CSIC) Madrid (Spain)
Design for Testability Theory and Practice Lecture 11: BIST
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 251 Lecture 25 Built-In Self-Testing Pattern Generation and Response Compaction n Motivation and economics.
Embedded Hardware and Software Self-Testing Methodologies for Processor Cores Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, and Ying Chen Design Automation.
6/17/2015Spectral Testing1 Spectral Testing of Digital Circuits An Embedded Tutorial Vishwani D. Agrawal Agere Systems Murray Hill, NJ 07974, USA
Jan. 9, 2007 VLSI Design Conference Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.
Fall 2006, Nov. 30 ELEC / Lecture 12 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Test Power Vishwani D.
9/21/04ELEC / Class Projects 1 ELEC / /Fall 2004 Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and.
Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Fault Simulation Vishwani D. Agrawal James J.
Spring 07, Jan 25 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 VLSI System DFT Vishwani D. Agrawal James J. Danaher.
Lecture 27 Memory and Delay-Fault Built-In Self-Testing
ELEC 7250 – VLSI Testing (Spring 2005) Place and Time: Broun 235, Tuesday/Thursday, 11:00AM—12:15PM Catalog data: ELEC VLSI Testing (3) Lec. 3. Pr.,
Testing of Logic Circuits. 2 Outline  Testing –Logic Verification –Silicon Debug –Manufacturing Test  Fault Models  Observability and Controllability.
Ugur Kalay, Marek Perkowski, Douglas Hall Universally Testable AND-EXOR Networks Portland State University Speaker: Alan Mishchenko.
Dominance Fault Collapsing of Combinational Circuits By Kalpesh Shetye & Kapil Gore ELEC 7250, Spring 2004.
11/17/04VLSI Design & Test Seminar: Spectral Testing 1 Spectral Testing Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer.
ELEN 468 Lecture 251 ELEN 468 Advanced Logic Design Lecture 25 Built-in Self Test.
TOPIC - BIST architectures I
3. Built-In Self Test (BIST): Periodical Off-Line Test on the Field 3.1 General Structure Unit Under Test Data Compressor Data Generator Comparator Display.
March 6, th Southeastern Symposium on System Theory1 Transition Delay Fault Testing of Microprocessors by Spectral Method Nitin Yogi and Vishwani.
BIST AND DATA COMPRESSION 1 JTAG COURSE spring 2006 Andrei Otcheretianski.
Spring 07, Jan 30 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 SOC Test Scheduling Vishwani D. Agrawal James.
Generating Random Numbers in Hardware. Two types of random numbers used in computing: --”true” random numbers: ++generated from a physical source (e.g.,
Testimise projekteerimine: Labor 2 BIST Optimization
Unit IV Self-Test and Test Algorithms
Muralidharan Venkatasubramanian Vishwani D. Agrawal
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS Built-In Self-Test (BIST) - 1.
1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS
Test pattern generator is BIST scan chains TESTGENERATOR COMPACOMPACCTTOORRCOMPACOMPACCTTOORRCTOR Control.
Linear Feedback Shift Register. 2 Linear Feedback Shift Registers (LFSRs) These are n-bit counters exhibiting pseudo-random behavior. Built from simple.
Page 1EL/CCUT T.-C. Huang May 2004 TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech.
Vishwani D. Agrawal Auburn University, Dept. of Elec. & Comp. Engg. Auburn, AL 36849, U.S.A. Nitin Yogi NVIDIA Corporation, Santa Clara, CA th.
TOPIC : Signature Analysis. Introduction Signature analysis is a compression technique based on the concept of (CRC) Cyclic Redundancy Checking It realized.
BIST Pattern Generator inserter using Cellular Automata By Jeffrey Dwoskin Project for Testing of ULSI Circuits, Spring 2002, Rutgers University 5/15/02.
Mixed-Mode BIST Based on Column Matching Petr Fišer.
Built-In Self Test (BIST).  1. Introduction  2. Pattern Generation  3. Signature Analysis  4. BIST Architectures  5. Summary Outline.
Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 1 Raimund Ubar N.Mazurova, J.Smahtina, E.Orasson, J.Raik Tallinn Technical University.
TOPIC : RTD, SST UNIT 5 : BIST and BIST Architectures Module 5.2 Specific BIST Architectures.
November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan1 Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns Nitin Yogi.
ELEC 7950 – VLSI Design and Test Seminar
POWER OPTIMIZATION IN RANDOM PATTERN GENERATOR By D.Girish Kumar 108W1D8007.
TITLE : types of BIST MODULE 5.1 BIST basics
July 10, th VLSI Design and Test Symposium1 BIST / Test-Decompressor Design using Combinational Test Spectrum Nitin Yogi Vishwani D. Agrawal Auburn.
Speaker: Nansen Huang VLSI Design and Test Seminar (ELEC ) March 9, 2016 Simulation-Based Equivalence Checking.
Hardware Testing and Designing for Testability
VLSI Testing Lecture 6: Fault Simulation
VLSI Testing Lecture 14: Built-In Self-Test
Motivation and economics Definitions
VLSI Testing Lecture 6: Fault Simulation
Sungho Kang Yonsei University
Testing in the Fourth Dimension
Lecture 26 Logic BIST Architectures
Mixed-Mode BIST Based on Column Matching
Motivation and economics Definitions
Presentation transcript:

Comparison of LFSR and CA for BIST Sachin Dhingra ELEC 7250: VLSI Testing 4/26/05 Dhingra: ELEC7250

Introduction Built-In Self Test Implementation of BIST Circuit capable of testing itself Two major components Test Pattern Generator Output Response Analyzer Implementation of BIST Linear Feedback Shift Register (LFSR) Shift Register with feedback path linearly related to the nodes using XOR gates Cellular Automata (CA) A collection of nodes logically related to their neighbors using XOR gates 4/26/05 Dhingra: ELEC7250

Built-In Self Test Test Mode Normal Operation System Inputs System Input Circuit Outputs Isolation Under Circuitry Test Test Output Pattern Response Generator Analyzer Test Controller TPG generates pseudo – random test vectors Input Isolation Circuitry isolates the normal system inputs from the CUT Output Response Analyzer performs polynomial division for test data compaction (signature analysis) 4/26/05 Dhingra: ELEC7250

Linear Feedback Shift Register (LFSR) Two Types External Feedback Internal Feedback Characteristic Polynomial All zero state is invalid Max. Sequence Length = 2n – 1 Primitive and Non-primitive Reciprocal of primitive polynomial is also primitive P*(x) = xnP(1/x) Compact Design Less than one gate per node Parallel Pattern generation Signature Analysis Signature Analysis Register (SAR) Multiple Input Signature Register (MISR) P (x) = x0 + x1 + x3 + x4 4/26/05 Dhingra: ELEC7250

Cellular Automata (CA) Rule 150 Rule 90 Rule 90 Rule 90 Null boundary condition One-Dimensional Linear CA Linear Hybrid Cellular Automata (LHCA) Linear Cellular Automata Register (LCAR) “Rules” define the logical relationship of a node with its neighbors Rule 90 xi(t+1) = xi-1(t)  xi+1(t) Rule 150 xi(t+1) = xi-1(t)  xi(t)  xi+1(t) Combination of Rules ≡ Characteristic Polynomial of LFSRs Boundary Condition Null Boundary Condition – No Feedback ⇒ Faster Cyclic Boundary Condition – Feedback ⇒ Slower Highly Random Vectors 4/26/05 Dhingra: ELEC7250

Comparison Characteristic LFSR CA Area Overhead Max. Length Sequence Least Less than one Gate/node Higher than LFSR One Gate/node Max. Length Sequence Easy to implement Well defined P(x) Harder to implement Combination of rules not well defined Performance Lower – External Feedback XOR gates in Feedback Higher – Internal Feedback Max. one gate/path High No gates in feedback Parallel Pattern Randomness Low Shifting of Data Logical relation with neighbors Stuck-at-fault detection Stuck-open and Delay fault Detection Less number of transitions Higher number of transitions due to higher randomness CAD friendliness No Nodes cannot be cascaded Yes Nodes can be easily cascaded Signature Aliasing Higher Probability Lower Probability 4/26/05 Dhingra: ELEC7250

Summary and Conclusion LFSRs are more popular because of their compact and simple design CAs are more complex to design but provide patterns with higher randomness CAs perform better in detection of faults such as stuck-open or delay faults, which need two-pattern testing In applications where area overhead is a big concern, LFSRs prove to be a better choice CAs provide a good alternative for LFSRs when high fault coverage is needed 4/26/05 Dhingra: ELEC7250

References M.L. Bushnell, V.D. Agrawal, Essentials of Electronics Testing for Digital, Memory & Mixed Signal VLSI Circuits, Kluwer Academic Publishers, Boston MA, 2000 C. Stroud, A Designer’s Guide to Built-In Self-Test, Kluwer Academic Publishers, Boston MA, 2002 S. Zhang et. al, “Why cellular automata are better than LFSRs as built-in self-test generators for sequential-type faults”, IEEE International Symposium on Circuits and Systems, Vol. 1, pp 69-72, 1994 P.D. Hortensius et. al, “Cellular automata-based pseudorandom number generators for built-in self-test,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 8, pp 842 - 859, 1989 K. Furuya, E.J. McCluskey, “Two-Pattern test capabilities of autonomous TPG circuits,” Proc. of International Test Conference, pp 704 – 711, 1991. L.T. Wang, E.J. McCluskey, “Circuits for Pseudoexhaustive Test Pattern Generation,” Proc. IEEE International Conference on Computer-Aided Design of Integrated Circuits and Systems, Vol. 7, pp. 1068 – 1080, 1988 P.D. Hortensius et. al, “Cellular automata-based signature analysis for built-in self-test,” IEEE Transactions on Computers, Vol. 39, pp. 1273 – 1283, 1990 K. Furuya et. al, “Evaluations of various TPG circuits for use in two-pattern testing,” Proceedings of the Third Asian Test Symposium, pp. 242 – 247, 1994 M. Serra, et. al, “The Analysis of One Dimensional Linear Cellular Automata and Their Aliasing Properties,” IEEE Trans. on CAD, pp. 767-778, 1990 4/26/05 Dhingra: ELEC7250