L15 – Control & Execution 1 Comp 411 – Spring /25/08 Control & Execution Finite State Machines for Control MIPS Execution

L15 – Control & Execution 2 Comp 411 – Spring /25/08 Synchronous Systems Latch Combinational logic Latch leading edge trailing edge On the leading edge of the clock, the input of a latch is transferred to the output and held. We must be sure the combinational logic has settled before the next leading clock edge. Clock data

L15 – Control & Execution 3 Comp 411 – Spring /25/08 Asynchronous Systems Latch Combinational logic Latch data valid No clock! The data carries a “valid” signal along with it System goes at greatest possible speed. Only “computes” when necessary. Everything we look at in this class will be synchronous  My specialization!

L15 – Control & Execution 4 Comp 411 – Spring /25/08 Fetching Sequential Instructions PCPC 4 Read Address Instruction Memory How about branch?

L15 – Control & Execution 5 Comp 411 – Spring /25/08 Datapath for R-type Instructions Read Reg Read Reg. 2 Write Reg. Write Data data 1 data 2 3 ALU Operation Inst Bits Inst Bits Inst Bits RegWrite 32

L15 – Control & Execution 6 Comp 411 – Spring /25/08 Fun with MUXes Select 0 In 3 In 2 Select 0 In 1 In 0 Select 1 Out Remember the MUX? This will route 1 of 4 different 1 bit values to the output.

L15 – Control & Execution 7 Comp 411 – Spring /25/08 MUX Blocks Out 210 Select Input 8 3 Select InOut The select signal determines which of the inputs is connected to the output

L15 – Control & Execution 8 Comp 411 – Spring /25/08 Inside there is a 32 way MUX per bit Register 0 Register 1 Register 2 Register 3 Register 4 Register... Register 30 Register to1 MUX Read Reg 1 Data 1 For EACH bit in the 32 bit register LOT’S OF CONNECTIONS! And this is just one port! 5

L15 – Control & Execution 9 Comp 411 – Spring /25/08 Our Register File has 3 ports Read Reg Read Reg. 2 Write Reg. Write Data data 1 data 2 Inst Bits Inst Bits Inst Bits RegWrite 32 2 Read Ports 1 Write Port REALLY LOTS OF CONNECTIONS! This is one reason we have only a small number of registers What’s another reason?

L15 – Control & Execution 10 Comp 411 – Spring /25/08 Implementing Logical Functions Suppose we want to map M input bits to N output bits For example, we need to take the OPCODE field from the instruction and determine what OPERATION to send to the ALU. 3 ALU Operation (8 different ops) 32 Map to ALU op OPCODE bits from instruction

L15 – Control & Execution 11 Comp 411 – Spring /25/08 We can get 1 bit out with a MUX Out 210 Select Input Put the INPUT HERE Wire these to HIGH or LOW depending on the value you want OUT for that INPUT For example, 3 input AND has INPUT7 wired HIGH and all the others wired LOW.

L15 – Control & Execution 12 Comp 411 – Spring /25/08 Or use a ROM Read-Only Memory M-bit Address N-bit Result

L15 – Control & Execution 13 Comp 411 – Spring /25/08 Or use a PLA AND Array M-bit Input OR Array N-bit Output Product Terms Think of the SUM of PRODUCTS form. The AND Array generates the products of various input bits The OR Array combines the products into various outputs Programmable Logic Array

L15 – Control & Execution 14 Comp 411 – Spring /25/08 Finite State Machines A set of STATES A set of INPUTS A set of OUTPUTS A function to map the STATE and the INPUT into the next STATE and an OUTPUT Remember automata?

L15 – Control & Execution 15 Comp 411 – Spring /25/08 Traffic Light Controller G E/W R N/S Y E/W R N/S R E/W G N/S R E/W Y N/S

L15 – Control & Execution 16 Comp 411 – Spring /25/08 Implementing a FSM State (flipflop) Function (comb. logic) Inputs Outputs Clock

L15 – Control & Execution 17 Comp 411 – Spring /25/08 Example: Recognizing Numbers Recognize the regular expression for floating point numbers [ \t]* [-+]?[0-9]*(. [0-9]*)? (e[-+]?[0–9]+)? Examples: e e “a” matches itself “[abc]” matches one of a, b, or c “[a-z]” matches one of a, b, c, d,..., x, y, or z “0*” matches zero or more 0’s (“”, “0”, “00”, “0000”) “Z?” matches zero or 1 Z’s

L15 – Control & Execution 18 Comp 411 – Spring /25/08 FSM Diagram start ‘ ’ sign ‘+’ ‘-’ whole ‘0’ – ‘9’ frac ‘.’ ‘0’ – ‘9’ exp ‘e’ ‘0’ – ‘9’ done ‘ ’

L15 – Control & Execution 19 Comp 411 – Spring /25/08 FSM Table IN : STATE  NEW STATE ‘ ’ : start  start ‘0’ | ‘1’ |... | ‘9’ : start  whole ‘+’ | ‘-’ : start  sign ‘.’ : start  frac ‘0’ | ‘1’ |... | ‘9’ : sign  whole ‘.’ : sign  frac ‘0’ | ‘1’ |... | ‘9’ : whole  whole ‘.’ : whole  frac ‘ ’ : whole  done ‘e’ : whole  exp ‘e’ : frac  exp ‘0’ | ‘1’ |... | ‘9’ : frac  frac ‘ ’ : frac  done ‘0’ | ‘1’ |... | ‘9’ : exp  exp ‘ ’ : exp  done STATE ASSIGNMENTS start = 0 = 000 sign = 1 = 001 whole = 2 = 010 frac = 3 = 011 exp = 4 = 100 done = 5 = 101 error = 6 = 110

L15 – Control & Execution 20 Comp 411 – Spring /25/08 FSM Implementation ROM or PLA or comb. logic state 3 8 char in error ok 3 Our PLA has: 11 inputs 5 outputs

L15 – Control & Execution 21 Comp 411 – Spring /25/08 FSM Summary With JUST a register and some logic, we can implement complicated sequential functions like recognizing a FP number. This is useful in its own right for compilers, input routines, etc. The reason we’re looking at it here is to see how designers implement the complicated sequences of events required to implement instructions Think of the OP-CODE as playing the role of the input character in the recognizer. The character AND the state determine the next state (and action).

L15 – Control & Execution 22 Comp 411 – Spring /25/08 Five Execution Steps 1. Instruction Fetch 2. Instruction Decode and Register Fetch 3. Execution, Memory Address Computation, or Branch Completion 4. Memory Access or R-type instruction completion 5. Memory Read Completion INSTRUCTIONS TAKE FROM CYCLES! A FSM looks at the op-code to determine how many...

L15 – Control & Execution 23 Comp 411 – Spring /25/08 Use PC to get instruction and put it in the Instruction Register. Increment the PC by 4 and put the result back in the PC. Can be described succinctly using RTL "Register-Transfer Language" IR = Memory[PC]; IR is “Instruction Register” PC = PC + 4; What is the advantage of updating the PC now? Step 1: Instruction Fetch

L15 – Control & Execution 24 Comp 411 – Spring /25/08 Read registers rs and rt in case we need them Compute the branch address in case the instruction is a branch RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC + (sign-extend(IR[15-0]) << 2); We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic) Step 2: Instruction Decode and Register Fetch

L15 – Control & Execution 25 Comp 411 – Spring /25/08 ALU is performing one of three functions, based on instruction type Memory Reference: ALUOut = A + sign-extend(IR[15-0]); R-type: ALUOut = A op B; Branch: if (A==B) PC = ALUOut; Step 3 (instruction dependent)

L15 – Control & Execution 26 Comp 411 – Spring /25/08 Loads and stores access memory MDR = Memory[ALUOut]; MDR is Memory Data Register or Memory[ALUOut] = B; R-type instructions finish Reg[IR[15-11]] = ALUOut; Step 4 (R-type or memory-access)

L15 – Control & Execution 27 Comp 411 – Spring /25/08 Reg[IR[20-16]]= MDR; Step 5 Memory Read Completion

L15 – Control & Execution 28 Comp 411 – Spring /25/08 Summary: