Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Slides:

Advertisements

Similar presentations

Digital Integrated Circuits© Prentice Hall 1995 Design Rules Jan M. Rabaey Design Rules.

Advertisements

CMOS Fabrication EMT 251.

Lecture 0: Introduction

Simplified Example of a LOCOS Fabrication Process

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Digital Integrated Circuits A Design Perspective Manufacturing Process July 30, 2002.

CMOS Process at a Glance

VLSI Design Lecture 2: Basic Fabrication Steps and Layout

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 CMOS Process Manufacturing Process.

Introduction to CMOS VLSI Design Lecture 0: Introduction

Prelab: MOS gates and layout

CMOS Technology: How are chips fabricated?

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,

Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.

CSE477 L05 IC Manufacturing.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 05: IC Manufacturing Mary Jane Irwin (

Device Fabrication Example

Introduction Integrated circuits: many transistors on one chip.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

CMOS Process Integration ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May March 25, 2004.

Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.

Manufacturing Process

Module-3 (MOS designs,Stick Diagrams,Designrules)

CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.

Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.

1. A clean single crystal silicon (Si) wafer which is doped n-type (ColumnV elements of the periodic table). MOS devices are typically fabricated on a,

IC Process Integration

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Chapter 2 Manufacturing Process March 7, 2003.

ECE484: Digital VLSI Design Fall 2010 Lecture: IC Manufacturing

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTR week2-1 Lecture 4 Transistor as Switch Jan

Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall Chapter 9 IC Fabrication Process Overview.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.

Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.

Lecture 24a, Slide 1EECS40, Fall 2004Prof. White Lecture #24a OUTLINE Device isolation methods Electrical contacts to Si Mask layout conventions Process.

Fabrication Technology(1)

Digital Integrated Circuit Design

Lecture 23 OUTLINE The MOSFET (cont’d) Drain-induced effects Source/drain structure CMOS technology Reading: Pierret 19.1,19.2; Hu 6.10, 7.3 Optional Reading:

Introduction EE1411 Design Rules. EE1412 3D Perspective Polysilicon Aluminum.

STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.

Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Digital Integrated Circuits A Design Perspective Manufacturing Process Jan M. Rabaey Anantha Chandrakasan.

CMOS Fabrication nMOS pMOS.

IC Fabrication/Process

NMOS FABRICATION 1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities.

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits Adapted from EECS 141 copyright UCB 1996 Manufacturing Process תהליך CMOS פרופ ’ יוסי שחם המחלקה לאלקטרוניקה פיזיקלית אוניברסיטת.

Purpose of design rules:

1 Overview of Fabrication Processes of MOSFETs and Layout Design Rules.

Dynamic Behavior of MOS Transistor. The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap.

CMOS VLSI Design Introduction

Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 LECTURE 9: KEEE 4425 WEEK 7 CMOS LAYOUT AND STICK DIAGRAM (Cont’d)

CMOS VLSI Fabrication.

STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.

CMOS FABRICATION.

EE141 Manufacturing 1 Chapter 2 Manufacturing Process and CMOS Circuit Layout 1 st rev. : March 7, nd rev. : April 10, 2003.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.

Out Line of Discussion on VLSI Design Basics

CMOS Fabrication EMT 251.

CSE477 L05 IC Manufacturing.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 05: IC Manufacturing Mary Jane Irwin (

IC Manufactured Done by: Engineer Ahmad Haitham.

Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56

Manufacturing Process I

Chapter 1 & Chapter 3.

Design Rule EMT 251.

Digital Integrated Circuits A Design Perspective

Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si

Manufacturing Process I

VLSI Lay-out Design.

V.Navaneethakrishnan Dept. of ECE, CCET

Manufacturing Process I

Presentation transcript:

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Process

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Inverter Layout

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Patterning on Si

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Semiconductor fabrication (1) 2

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Semiconductor Fabrication (2) 1 4 3

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Semiconductor Fabrication (3) 3 3

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Semiconductor Fabrication (4) END 4

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Circuit Under Design This two-inverter circuit (of Figure 3.25 in the text) will be manufactured in a twin-well process.

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Circuit Layout Inverter 2Inverter 1 D1D1 D2D2 D4D4 S2S2 D3D3 S4S4 S1S1 S3S3 GND Vdd G1G1 G2G2G4G4 G3G3 pMOS-2 pMOS-1 nMOS-2 nMOS-1 IN1OUT2OUT1IN2 IN2=OUT1 B4 B2 B3 B1 Inverter 1 nMOS-1 pMOS-1 Inverter 2 nMOS-2 pMOS-2

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Start Material Starting wafer: n-type with doping level = /cm 3 * Cross-sections will be shown along vertical line A-A’ Si n-type nMOS pMOS A A’A’ A A’A’

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process N-well Construction (1) Oxidize wafer (2) Deposit silicon nitride (3) Deposit photoresist Si n-type photoresist silicon nitride silicon dioxide nMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process N-well Construction (4) Expose resist using n-well mask Si n type Exposed resist nMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process N-well Construction (5) Develop resist (6) Etch nitride and (7) Grow thick oxide Si n type nMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process N-well Construction (8) Implant n-dopants (phosphorus) (up to 1.5  m deep) thick oxide n-well Si n type nMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process P-well Construction Repeat previous steps Si n type n-wellp-well pMOSnMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Grow Gate Oxide Gate oxide 55 nm thin Si n type n-wellp-well pMOSnMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Grow Thick Field Oxide Uses Active Area mask Is followed by threshold-adjusting implants Field Oxide 0.9  m thick Si n type n-wellp-well pMOSnMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Polysilicon layer Polysilicon Deposition Si n type n-wellp-well pMOS nMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Source-Drain Implants photoresist Si n type n-wellp-well pMOS nMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Source-Drain Implants Si n type n-wellp-well pMOS nMOS GB S DBGSD pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Contact-Hole Definition (1) Deposit inter-level Dielectric (SiO 2 ) — 0.75  m (2) Define contact opening using contact mask Si n type n-wellp-well pMOS nMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Aluminum-1 Layer Aluminum evaporated (0.8  m thick) followed by other metal layers and glass GB G S D B GSD IN OUT pMOS nMOS VddGND IN OUT nMOS pMOS

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Advanced Metalization

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Intel 0.09  m Generation

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Downsizing MOSFET below 0.1  m

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Design Rules

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Design Rules l Interface between designer and process engineer l Guidelines for constructing process masks l Unit dimension: Minimum line width »scalable design rules: lambda parameter »absolute dimensions (micron rules)

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Intra-Layer Design Rules Metal2 4 3

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Transistor Layout Transistor

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Via’s and Contacts

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Select Layer