ELEN468 Lecture 11 ELEN468 Advanced Logic Design Lecture 1Introduction

ELEN468 Lecture 12 Chips Everywhere!

ELEN468 Lecture 13 Market Size By 8/12/06, 25 th anniversary of IBM PC 1.5 billion PCs sold world wide $3,100 billions worth Information technology accounts for 3% of US GDP 25% of GDP growth are information technology companies are Electronics industry $1T Semiconductor industry $200B

ELEN468 Lecture 14 Who is this Guy? Moore’s Law: Number of transistors doubles every 18 months

ELEN468 Lecture 15 Analogue In 1978, a commercial flight between New York and Paris cost $900 and took 7 hours. If Moore’s Law were applied to the airline industry, today that flight could cost Less than 1 penny Less than 1 second

ELEN468 Lecture 16 What are inside a chip? A chip may include: Hundreds of millions of transistors ~Mb embedded SRAM DSP, IP cores PLL, ADC, DAC… 100+ internal clocks … … Design issues: Speed Power Area Signal integrity Process variation Manufacturing yield … … Source: Byran Preas

ELEN468 Lecture 17 Technology Roadmap for Semiconductors Wiring levels Power (W) Clock freq. (MHz) 2854M1427M714M357M178M112M# transistors Year Technology (nm) Technology  minimal transistor feature size

ELEN468 Lecture 18 Chip Design Productivity Crisis x x x x x x x 21%/Yr. Productivity growth rate x 58%/Yr. Complexity growth rate ,000 10, ,000 1,000,000 10,000, ,000 10, ,000 1,000,000 10,000, ,000,000 Transistors/Chip (K) Transistor/Staff-Month 2003 Source NTRS’97

ELEN468 Lecture 19 Solutions Apply CAD tools High level abstraction Verilog Learn Verilog !

ELEN468 Lecture 110 Basic Design Flow System design Instruction set for processor Hardware/software partition Memory, cache Logic design Logic synthesis Logic optimization Technology mapping Physical design Floorplanning Placement Routing System/Architectural Design Logic Design Physical Design/Layout Fabrication

ELEN468 Lecture 111 Design Cycles System/Architectural Design Logic Design Physical Design/Layout Fabrication HDL Verification/Simulation Parasitic Extraction Testing

ELEN468 Lecture 112 Design and Technology Styles Custom design Mostly manual design, long design cycle High performance, high volume Microprocessors, analog, leaf cells, IP … Standard cell Pre-designed cells, CAD, short design cycle Medium performance, ASIC FPGA/PLD Pre-fabricated, fast automated design, low cost Prototyping, reconfigurable computing

ELEN468 Lecture 113 Why do we need HDLs ? HDL can describe both circuit structure and behavior Schematics describe only circuit structure C language describes only behaviors Provide high level abstraction to speed up design High portability and readability Enable rapid prototyping Support different hardware styles

ELEN468 Lecture 114 What do we need from HDLs ? Describe Combinational logic Level sensitive storage devices Edge-triggered storage devices Provide different levels of abstraction and support hierarchical design System level RTL level Gate level Transistor level Physical level Support for hardware concurrency

ELEN468 Lecture 115 Two major HDLs Verilog Slightly better at gate/transistor level Language style close to C/C++ Pre-defined data type, easy to use VHDL Slightly better at system level Language style close to Pascal User-defined data type, more flexible Equally effective, personal preference

ELEN468 Lecture 116 Schematic Design a b Add_half sum c_out sum = a  b c_out = a b a b sum c_out c_out_bar

ELEN468 Lecture 117 Module portsModule name Verilog keywords Taste of Verilog module Add_half ( sum, c_out, a, b ); inputa, b; outputsum, c_out; wire c_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule Declaration of port modes Declaration of internal signal Instantiation of primitive gates c_out a b sum c_out_bar

ELEN468 Lecture 118 Behavioral Description module Add_half ( sum, c_out, a, b ); inputa, b; outputsum, c_out; reg sum, c_out; ( a or b ) begin sum = a ^ b;// Exclusive or c_out = a & b;// And end endmodule a b Add_half sum c_out

ELEN468 Lecture 119 Example of Flip-flop module Flip_flop ( q, data_in, clk, rst ); input data_in, clk, rst; output q; reg q; ( posedge clk ) begin if ( rst == 1) q = 0; else q = data_in; end endmodule data_inq rst clk Declaration of synchronous behavior Procedural statement

ELEN468 Lecture 120 Conclusion VLSI Chips Chip design flow Chip design styles Why do we need HDLs ? What do we need from HDLs ? Examples of Verilog HDL