Update on JEM FPGA coding. Carsten NödingJohannes Gutenberg-Universität Mainz JEM block diagramm.

Slides:



Advertisements
Similar presentations
Components of a computer system
Advertisements

Nios Multi Processor Ethernet Embedded Platform Final Presentation
Enhanced matrix multiplication algorithm for FPGA Tamás Herendi, S. Roland Major UDT2012.
7-5 Microoperation An elementary operations performed on data stored in registers or in memory. Transfer Arithmetic Logic: perform bit manipulation on.
ECE 734: Project Presentation Pankhuri May 8, 2013 Pankhuri May 8, point FFT Algorithm for OFDM Applications using 8-point DFT processor (radix-8)
A self-reconfiguring platform Brandon Blodget,Philip James- Roxby, Eric Keller, Scott McMillan, Prasanna Sundararajan.
Uli Schäfer JEM Status and plans Hardware status JEM0 Hardware status JEM1 Plans.
Jet algorithm/FPGA by Attila Hidvégi. Content Jet algorithm Jet-FPGA – Changes – Results – Analysing the inputs Tests at RAL Summary and Outlook.
JET Algorithm Attila Hidvégi. Overview FIO scan in crate environment JET Algorithm –Hardware tests (on JEM 0.2) –Results and problems –Ongoing work on.
Uli Schäfer JEM Plans Status (summary) Further standalone tests Sub-slice test programme JEM re-design Slice test.
Lecture 26: Reconfigurable Computing May 11, 2004 ECE 669 Parallel Computer Architecture Reconfigurable Computing.
Moving NN Triggers to Level-1 at LHC Rates Triggering Problem in HEP Adopted neural solutions Specifications for Level 1 Triggering Hardware Implementation.
1 Performed by: Lin Ilia Khinich Fanny Instructor: Fiksman Eugene המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון - מכון טכנולוגי.
JEM input processor stand-alone tests Andrey Belkin Uni Mainz 7th November 2003.
Uli Schäfer 1 JEM1: Status and plans Hardware status Firmware status Plans.
Detector Array Controller Based on First Light First Light PICNIC Array Mux PICNIC Array Mux Image of ESO Messenger Front Page M.Meyer June 05 NGC High.
Uli Schäfer JEM Status and plans RAL test results Hardware status Firmware Plans.
Uli Schäfer JEM hardware / test JEM0 test programme Mainz standalone RAL sub-slice test JEM re-design Heidelberg slice test.
Uli Schäfer JEM Status and plans Firmware Hardware status JEM1 Plans.
Uli Schäfer JEM Status and plans Algorithms Hardware JEM0, JEM1 Tests Plans.
Lecture 7 Lecture 7: Hardware/Software Systems on the XUP Board ECE 412: Microcomputer Laboratory.
Software Development and Software Loading in Embedded Systems.
GallagherP188/MAPLD20041 Accelerating DSP Algorithms Using FPGAs Sean Gallagher DSP Specialist Xilinx Inc.
GPGPU platforms GP - General Purpose computation using GPU
Booster Cogging Teststand Progress Update Kiyomi Seiya, Alex Waller, Craig Drennan August 22, 2012.
Study of AES Encryption/Decription Optimizations Nathan Windels.
Input/Output. Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower.
Christian Steinle, University of Mannheim, Institute of Computer Engineering1 L1 Tracking – Status CBMROOT And Realisation Christian Steinle, Andreas Kugel,
Revised: Aug 1, ECE 263 Embedded System Design Lesson 1 68HC12 Overview.
JEP HW status and FW integration plans Uli Schaefer and Pawel Plucinski Johannes-Gutenberg Universitaet Mainz Stockholm University.
Uli Schäfer 1 JEM configurator progress FPGAs are RAM-based programmable logic devices Need to be loaded with a ‘configuration’ after power-up, so as to.
1 Fly – A Modifiable Hardware Compiler C. H. Ho 1, P.H.W. Leong 1, K.H. Tsoi 1, R. Ludewig 2, P. Zipf 2, A.G. Oritz 2 and M. Glesner 2 1 Department of.
25 March 2011Ian Brawn1 Potential Enhancements to the XS Trigger Firmware Current Implementation Potential Enhancements –Functional overview –Resource.
Algorithm and Programming Considerations for Embedded Reconfigurable Computers Russell Duren, Associate Professor Engineering And Computer Science Baylor.
Field Programmable Port Extender (FPX) 1 Modular Design Techniques for the FPX.
ATLAS Trigger / current L1Calo Uli Schäfer 1 Jet/Energy module calo µ CTP L1.
Fast Fault Finder A Machine Protection Component.
Lisbon, 23/10/03TSS: ATLAS L1 Simulation / CTP1 From CTP-D to CTP Ideas from the top of my head Th. Schörner-Sadenius, U Hamburg I basically looked through.
ALU (Continued) Computer Architecture (Fall 2006).
Copyright © 2004, Dillon Engineering Inc. All Rights Reserved. An Efficient Architecture for Ultra Long FFTs in FPGAs and ASICs  Architecture optimized.
ESS | FPGA for Dummies | | Maurizio Donna FPGA for Dummies Basic FPGA architecture.
THE MICROPROCESSOR A microprocessor is a single chip of silicon that performs all of the essential functions of a computer central processor unit (CPU)
2001/02/16TGC off-detector PDR1 Sector Logic Status Report Design Prototype-(-1) Prototype-0 Schedule.
Jet algorithm and Jet FPGA by Attila Hidvégi. Content Status of the Jet algorithm New design for the Jet FPGA on JEM-1.0 Jet CMM firmware Summary Outlook.
University of Sargodha, Lahore Campus Prepared by Ali Saeed.
Input Output Techniques Programmed Interrupt driven Direct Memory Access (DMA)
1 Level 1 Pre Processor and Interface L1PPI Guido Haefeli L1 Review 14. June 2002.
Chapter 2 Data Manipulation © 2007 Pearson Addison-Wesley. All rights reserved.
JET Algorithm Attila Hidvégi. Overview FIO scan in crate environment JET Algorithm –Hardware tests (on JEM 0.2) –Results and problems –Some VHDL tips.
Interrupts and Exception Handling. Execution We are quite aware of the Fetch, Execute process of the control unit of the CPU –Fetch and instruction as.
Software tools for digital LLRF system integration at CERN 04/11/2015 LLRF15, Software tools2 Andy Butterworth Tom Levens, Andrey Pashnin, Anthony Rey.
1 Chapter 1 Basic Structures Of Computers. Computer : Introduction A computer is an electronic machine,devised for performing calculations and controlling.
Configuration and local monitoring
Computer Organization
ETE Digital Electronics
Author: Yun R. Qu, Shijie Zhou, and Viktor K. Prasanna Publisher:
Virtex-6 Investigations
ATLAS calorimeter and topological trigger upgrades for Phase 1
Sector logic firmware and G-link Merger board designs
Head-to-Head Xilinx Virtex-II Pro Altera Stratix 1.5v 130nm copper
CoBo - Different Boundaries & Different Options of
CS703 - Advanced Operating Systems
FPGA Implementation of Multicore AES 128/192/256
Implementation of the Jet Algorithm ATLAS Level-1 Calorimeter Trigger
ATLAS: Level-1 Calorimeter Trigger
Architecture Overview
INTRODUCTION TO COMPUTERS
Sector Processor Status Report
A Top-Level View Of Computer Function And Interconnection
Presentation transcript:

Update on JEM FPGA coding

Carsten NödingJohannes Gutenberg-Universität Mainz JEM block diagramm

Carsten NödingJohannes Gutenberg-Universität Mainz Input FPGA Changes since Birmingham Meeting: 256 slices deep playback memory can be written via consecutive single word transfers and read back code clean-up

Carsten NödingJohannes Gutenberg-Universität Mainz Main Processor

Carsten NödingJohannes Gutenberg-Universität Mainz E T,miss, E T

Carsten NödingJohannes Gutenberg-Universität Mainz Main Processor (1) Changes since Birmingham Meeting (only RTDP of energy tree): code clean-up Past: Conversion into E X and E Y was done in 16 LUT based multipliers using ROMs  Only changeable by loading a new configuration  Handling of INIT values for LUTs is annoying Latency of RTDP: 3 bunch crossings MHz, 25 % logic resources XCV600E-7-FG680C) [Logic resources needed for jet tree: %] Present: Multiplication is done using Block SelectRAM capabilities of Virtex-E  Changeable via consecutive VME read/write access  Easier handling, code easier to understand Latency: 4 bunch crossing MHz, 15 % logic resources of XCV600E- 7-FG680C)

Carsten NödingJohannes Gutenberg-Universität Mainz Main Processor (2) Future: Use Virtex-II device as Main Processor: Multiplication can done using embedded 18bit by 18bit multipliers  Accuracy is not worsened  Code can be easily adapted (just throw away half of it)  Latency: 2.5 bunch crossings

Carsten NödingJohannes Gutenberg-Universität Mainz Reorganisation of JEM Programming Model Changes since Birmingham Meeting: Added gaps in register offsets (especially around blocks of related ones, eg. jet thresholds)  things can be changed in the future without having to change the offsets used in any existing software  registers which belong together start at some nice boundary Module ID words start at address 0 of the module Added multiplication registers to store E T sin() and E T cos() results in BlockRAMs (Virtex-E)  same register can be used for storing sin() and cos() in Virtex-II devices “separate registers for separate things”  Programming Model has been approved by Murrough  Current version can be found in the latest JEM PDR available on the web

Carsten NödingJohannes Gutenberg-Universität Mainz Outlook Main task now: Test of JEM prototype