Analytical Thermal Placement for VLSI Lifetime Improvement and Minimum Performance Variation Andrew B. Kahng †, Sung-Mo Kang ‡, Wei Li ‡, Bao Liu † † UC San Diego ‡ UC Santa Cruz

Outline Background Modeling and Theoretical Results Analytical Thermal Placement Experiment Summary

VLSI On-Chip Temperature Scaling Pentium® proc P Year Power Density (W/cm2) Hot Plate Rocket Nozzle Nuclear Reactor Courtesy, Intel

Temperature Scaling: Why and How Scaling has led to temperature rise in VLSI  Higher integration  Higher clock frequency  Leakage power Cooling techniques are stagnant  Air ventilation  Liquid cooling Low power design  Power gating, clock gating, dynamic scheduling Placement

Chip Packaging Structures Heat dissipation through bulk silicon in wire bond packaging Devices and interconnects closer to heat sinks in flip chip packaging

Electrical analogue: RC Circuit  Thermal conductance G  Heat capacity C From Boltzmann’s Equation  p ( r ) power density  g ( r ) thermal conductivity Heat Dissipation Equations Poission’s Equation Purely Resistive Network DynamicStatic

Thermal Effects on Performance Higher temperature   Superlinear decrease of carrier mobility  Linear decrease of transistor threshold voltage  Increase or decrease of transistor output current depending on transistor threshold voltage, supply voltage, etc.  Increase of interconnect resistance

Circuit lifetime T f decreases superlinearly with rising temperature  Hot carriers  Oxide breakdown  Electromigration where  J current density  Q activation energy (1.0eV for copper)  k Boltzmann constant  T temperature  D given by device structure Thermal Effects on Circuit Lifetime

Previous Thermal Placers Objective:  Total on-chip temperature 1  Maximum on-chip temperature 23 Method:  Simulated annealing 34  Min-cut bi-partition 1 Thermal simulation  Compute thermal resistance matrix at each iteration Chao and Wong, Thermal placement for high performance multichip modules, ICCD, Chu and Wong, A matrix synthesis approach to thermal placement, ISPD, Cong, Wei, and Zhang, A thermal-driven floorplanning algorithm for 3D IC, ICCD, Tsai and Kang, Cell-level placement on improving substrate thermal distribution, IEEE Trans. CAD, 2000

Outline Background Modeling and Theoretical Results Analytical Thermal Placement Experiment Summary

Thermal Modeling  FDM (Finite Difference Method)  MOR (Model Order Reduction)  Heat source Boundary thermal resistor

Placement for minimum on-chip temperature at a specific spot is linear  How to locate current sources s.t. V o is minimized? Solved by greedy algorithm: Locate maximum current source with minimum resistance Objective and Complexity

Placement for minimum average on-chip temperature is linear  How to locate current sources s.t.  i V i is minimized? Solved by greedy algorithm: Locate maximum current source with minimum resistance Objective and Complexity

Placement for minimum maximum on-chip temperature is NP-hard  Reduces to the bi-partition problem: Given we have Objective and Complexity i=1,2 and i,j on the same side otherwise

Outline Background Modeling and Theoretical Results Analytical Thermal Placement Experiment Summary

Problem Formulation Given  Chip dimensions 0<x<a, 0<y<b, 0<z<d  Thermal parameters Thermal conductivity k on chip top Thermal conductivity k N on chip bottom Effective heat transfer coefficient h on chip bottom Ambient temperature T r  Cells C of power consumption P  Netlist N Find a cell placement which minimizes sum of total wirelength and maximum temperature

Analytical Placement Approximate the NP-hard placement problem as a nonlinear optimization problem Relax the non-overlapping constraint into a cell density unevenness penalty function Minimize relax legalize

A cell centered at (x c,y c ) of width w and height h distributes its area over a grid of points (x,y) where Cell Density Distribution -r/2 r/2 1 x Cell density -r/2 r/2 1 x Cell density -r r

Half perimeter wirelength Approximate min/max by logarithm of sum of exponents Smooth Wirelength Function

Analytical Thermal Placement Minimize where A, b, g are such that terms are comparative G -1 does not change during placement iteration

Congestion Penalty Function Minimize where If congested: sharper increase of penalty  stricter enhancement If not congested: no penalty  more relaxed

Outline Background Modeling and Theoretical Results Analytical Thermal Placement Experiment Summary

Experiment Setting We compare analytical thermal placement to thermal effect oblivious analytical placement APlace Two industry design test cases of gate array logic in 130nm and 180nm technologies Utilizati on 10.0W Total Power 180nm II 130nm I Techno logy #rows#blocks#cellsdesign

Thermal Placement Data Flow Thermal Simulation Netlist Thermal Resistances Chip Dimensions Material, Boundary Conditions Analytical Thermal Placement Power Profile Temperature Reduction

A Snapshot of Placement Result

Analytical Thermal Placement vs. Traditional Analytical Placement ATP APlace Placer (s)(%)(mm)(%)(K)  0.00 HPWL CPUMax Tempg Test case II: 180  m industry design of 7K cells Test case I: 130nm industry design of13K cells ATP APlace Placer (s)(%)(mm)(%)(K)   0.00 HPWL CPUMax Tempg

Outline Background Modeling and Theoretical Results Analytical Thermal Placement Experiment Summary

We propose analytical thermal placement and achieve 17.85% and 30.77% maximum on-chip temperature variation reduction and 4.61% and 0.45% wirelength reduction compared with the existing analytical placement for the two industry designs, respectively We present theoretical results on the complexity of specific spot temperature, average on-chip temperature, and maximum on-chip temperature minimum placement as linear, linear, and NP-hard Future directions  Thermal effect aware performance optimization  3-D thermal placement

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