1 Foundations for Understanding Achievable Design: Ground Truths, the Bookshelf, and Metrics Theme Summary

2 Mission Enable the understanding of achievable design

3 Precepts u System design is based on : –design optimization – prediction u GSRC must prove : –real collaboration (“combine strengths”) ; whole > sum of parts –critical mass and influence to create community-wide culture change –its effect on the real-world practice of design and test u This Theme’s answer: –ground truths –the bookshelf –metrics

4 1. Ground Truths u Fundamental facts and data points that anchor the process of bounding the achievable envelope of design –ground truths must be identified and propagated u Can be with respect to: –manufacturing process, materials, physical phenomena –specific CAD optimizations of circuit topology/embedding –system architecture and packaging u Are properly extrapolated via: –"inference chains" –response surface modeling and parameter optimization u Drive the EDA vision of future design issues, methodology –fundamental limits, fundamental truths, stakes in the ground –current distribution, inductance extraction, UDSM testing, …

5 Example Ground Truths u What is the maximum possible clock frequency for a given process and die size? u When does inductance matter? u What design tradeoffs must be made to maintain reasonable supply currents? u What is the necessary number of package pins/balls for power/ground distribution? u At what geometries, supply voltages will domino lose most advantages over static CMOS? u What is an optimum design strategy from a manufacturing cost point of view?

6 2. The Bookshelf u The Bookshelf –framework to enable shared, community-wide maintenance of state for key pieces of the (CAD algorithms) R&D leading edge –remove barriers to entry for algorithm research -- and adoption of algorithm research -- at the leading edge u Bookshelf Slot: “key problem for the VLSI CAD field” u Bookshelf = repository for leading-edge innovations -- and their implementations -- for solving this problem u Literally, publication medium + review process for implementations –electronic infrastructure permits archival, “arbitrarily large” publications –credit for leading-edge work via respectable, referable nature –facilitates review, returns for fixes to preserve quality –backed by other incentives, openness, culture change

7 The Bookshelf (cont.) u For given Bookshelf slot, several basic types of entries –canonical problem definition (e.g., C++ class + supporting packages) –reference solver implementations –benchmark data –heuristic evaluation and comparison methodology u Bookshelf framework allows : –improved effectiveness and impact of heuristic algorithm research in VLSI CAD –more rapid communication between research groups –more rapid adoption of research advances by industry –path to evolvable GSRC implementation flows/methodologies –implicit definition, testing of underlying data model

8 3. Metrics u Design optimization must be founded on –an understanding of what should be optimized by which heuristic –an understanding of design as a process u “Metrics” supports ideal of "measure, then improve” –design becomes less of an art and more of a formal discipline –design process optimization enabled through framework of recording, mining, measuring, diagnosing, and then improving u Infrastructure –hoped-for: “proactive” initiative from EDA vendors –reality: for now, will use Perl scripts around existing tool logfiles –guidance from designer and design tools R&D communities: (i) what should be measured, (ii) data mining / visualization / diagnosis infrastructure, (iii) project-specific design process data collection

9 Staffing u Andrew Kahng 100% u Wayne Dai 100% u Wojciech Maly 50% u Jason Cong 33% u Kurt Keutzer 20%

10 Ground Truths Status u Basic engine and infrastructure –2 Ph.D. students, one staff –dialogue with RPI, Georgia Tech, Berkeley, Rockwell, … –bring in experts to help define / vet models and rules chains u Key differentiators –models of optimizations (BIS/WS-optimized, multi-terminal global interconnects; block packing; optimal layer assignment, …) –cost modeling, cost implications of design decisions –flexible use model, platform independence, many “canned” previous studies, design of system with adoptability in mind u Working through key software issues: –software architecture (C++/Java, multi-platform) –engine, GUI codesign –flexible definition of rules chains, studies, etc.

11 The Bookshelf Status u Initial bookshelf slots: –hypergraph partitioning –block packing / floorplanning –standard-cell placement –single-tree interconnect synthesis/optimization –grid-graph based global routing u Extremely active convergence on data formats, tool linkages –UIC, UCLA, SUNY Binghamton, UCSC in initial loop –2 Ph.D. students + outsourcing to interested/engaged researchers –will likely end up being a practical driver for efforts toward GSRC- endorsed data model and API u Standards –standards (build system, platform, software, etc.) near-converged u Commercial backplane –tools (back-end implementation flow) from Synopsys, Cadence –compare against, integrate, mix-and-match with mini-flow above –industry data also sought

12 Metrics Status u Metrics infrastructure –substantial IP recently obtained from OxSigen LLC (used at Siemens) –Metrics warehouse: data model, schema, API, servlets –Metrics transmitter: applets to write metrics, embeddable in tools –Off-the-shelf standard components: Oracle8i, XML, Java, Chai –OxSigen scripts + extensions wrapped around today’s tool logfiles : metricizes the baseline (Synopsys/Cadence) GSRC back-end flow –1 Ph.D. student will do thesis on Metrics in EDA u Need more buy-in from EDA companies u Need more pull from EDA customers = GSRC sponsors

13 Future Plans u Ground truths system, GTX1.0 –GTX1.0: arbitrary tradeoff studies, parameter optimizations –platform-independent, GUI-enabled –accurate models of optimization effects in layers between individual wires/devices and system architecture –determine how correct/incorrect our views of ground truths may be (e.g., white papers on clock jitter/skew, wire estimation models, …) u Bookshelf –culture/behavior goals, standards: publicize, internalize, externalize –3-5 slots instantiated with entries from multiple investigators –mini-flow built around partitioning / soft-block packing / cell placement / interconnect opt / global routing u Metrics –integration of OxSigen IP –GSRC endorsement/proposal of standard Metrics schema and API –GSRC sites running metricized std implementation methodology