Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 4: Feb. 11 th Gate Level Design Overall Project Objective: Design an Air-Fuel Ratio Controller for a small gasoline engine with low emissions and low cost Design Manager: Steven Beigelmacher

Status Design Proposal (done) Architecture (done) High Level C Simulation Behavioral Verilog & Test Bench Final Algorithm & Major Functional Components Floorplan & Structural Verilog (done) Simulated successfully Gate Level Design Components finished, top-level nearly done. To be done Component Layout Chip Layout SPICE Simulation of Entire Chip

Design Decisions Bit designation of Control Rom All control signals finalized Using latches instead of registers in many cases

Structural Code

Structural Simulation

12bit Input Reg 8X10 SRAM Value Look-up 12bit Input Reg Engine Speed Manifold Pressure 12bit Input Reg Throttle Position Fixed Point Array Multiplier 2:1Mu x 12bit Output Register Control ROM 12bit Input Reg %Oxygen 7X4 SRAM Comparator Look-up 4:1Mux = R0 12bit Register Win Sin[0:1] 2:1Mu x Rcomp Sin[0:1] Index[0:4] Write R1 R2 RowComp[0]RowComp[1] Srow1 Srow2 RowComp[2] 3bit Reg Wcol Index[0:6] Write Rtable 2:1Mu x Scol ColTable[0:3] 2:1Mu x Scol Valid Wmult1 Wmult2 Smult 5bit State Reg Next[0:4] Wout PulseOut[0:11]

Results: Control Rom & Multiplier

Results: SRAM & Comparator

Floorplan Pin Distribution: 5 12-bit inputs 12-bit output 7-bit index input Clk, write, block, valid 8X10 SRAM Multiplier Comparator MUxMUx Control ROM 500µm 7X4 SRAM

Updated Transistor Count Registers (5 12-bit, shift)2,568 SRAMS (1 8x10, 1 7x4)6,720 Comparator410 MUXs (2)696 Control Logic1, bit FP Multiplier3,096 Decoders1,000 TOTAL difference 15,490

Problems Getting basic SRAMs to function Top-level schematic Time

Questions????