1 Petrify: Method and Tool for Synthesis of Asynchronous Controllers and Interfaces Jordi Cortadella (UPC, Barcelona, Spain), Mike Kishinevsky (Intel Strategic CAD Labs, Oregon), Alex Kondratyev (Berkeley Cadence Research Labs, CA), Luciano Lavagno (Politecnico di Torino, Italy ), Alex Yakovlev (University of Newcastle, UK)

ASYNC Tutorial on Petrify Method and Tool2 Outline Part 1: The Petrify Method –Overview of the Petrify synthesis flow –Specification: Signal Tranistion Graphs –State graph and next-state functions –State encoding –Implementation conditions –Speed-independent circuits Complex gates C-element architecture

ASYNC Tutorial on Petrify Method and Tool3 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

ASYNC Tutorial on Petrify Method and Tool4 x y z x+ x- y+ y- z+ z- Signal Transition Graph (STG) x y z Specification

ASYNC Tutorial on Petrify Method and Tool5 x y z x+ x- y+ y- z+ z- Token flow

ASYNC Tutorial on Petrify Method and Tool6 x+ x- y+ y- z+ z- xyz 000 x+ 100 y+ z+ y x y+ z- 010 y- State graph

ASYNC Tutorial on Petrify Method and Tool7 Next-state functions xyz 000 x+ 100 y+ z+ y x y+ z- 010 y-

ASYNC Tutorial on Petrify Method and Tool8 x z y Gate netlist

ASYNC Tutorial on Petrify Method and Tool9 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

ASYNC Tutorial on Petrify Method and Tool10 VME bus Device LDS LDTACK D DSr DSw DTACK VME Bus Controller Data Transceiver Bus DSr LDS LDTACK D DTACK Read Cycle

ASYNC Tutorial on Petrify Method and Tool11 STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

ASYNC Tutorial on Petrify Method and Tool12 Choice: Read and Write cycles DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK-DTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

ASYNC Tutorial on Petrify Method and Tool13 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

ASYNC Tutorial on Petrify Method and Tool14 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

ASYNC Tutorial on Petrify Method and Tool15 Circuit synthesis Goal: –Derive a hazard-free circuit under a given delay model and mode of operation

ASYNC Tutorial on Petrify Method and Tool16 Speed independence Delay model –Unbounded gate / environment delays –Certain wire delays shorter than certain paths in the circuit Conditions for implementability: –Consistency –Complete State Coding –Persistency

ASYNC Tutorial on Petrify Method and Tool17 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

ASYNC Tutorial on Petrify Method and Tool18 STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

ASYNC Tutorial on Petrify Method and Tool19 Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+

ASYNC Tutorial on Petrify Method and Tool20 Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS (DSr, DTACK, LDTACK, LDS, D)

ASYNC Tutorial on Petrify Method and Tool21 QR (LDS+) QR (LDS-) Excitation / Quiescent Regions ER (LDS+) ER (LDS-) LDS- LDS+ LDS-

ASYNC Tutorial on Petrify Method and Tool22 Next-state function 0  1 LDS- LDS+ LDS- 1  0 0  0 1 

ASYNC Tutorial on Petrify Method and Tool23 Karnaugh map for LDS DTACK DSr D LDTACK DTACK DSr D LDTACK LDS = 0 LDS = /1?

ASYNC Tutorial on Petrify Method and Tool24 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

ASYNC Tutorial on Petrify Method and Tool25 Concurrency reduction LDS- LDS+ LDS DSr+

ASYNC Tutorial on Petrify Method and Tool26 Concurrency reduction LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+

ASYNC Tutorial on Petrify Method and Tool27 State encoding conflicts LDS- LDTACK- LDTACK+ LDS

ASYNC Tutorial on Petrify Method and Tool28 Signal Insertion LDS- LDTACK- D- DSr- LDTACK+ LDS+ CSC- CSC

ASYNC Tutorial on Petrify Method and Tool29 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

ASYNC Tutorial on Petrify Method and Tool30 Complex-gate implementation

ASYNC Tutorial on Petrify Method and Tool31 Implementation conditions Consistency –Rising and falling transitions of each signal alternate in any trace Complete state coding (CSC) –Next-state functions correctly defined Persistency –No event can be disabled by another event (unless they are both inputs)

ASYNC Tutorial on Petrify Method and Tool32 Implementation conditions Consistency + CSC + persistency There exists a speed-independent circuit that implements the behavior of the STG (under the assumption that ay Boolean function can be implemented with one complex gate)

ASYNC Tutorial on Petrify Method and Tool33 Persistency a- c+ b+b+ b+b+ a c b a c b is this a pulse ? Speed independence  glitch-free output behavior under any delay

a+ b+ c+ d+ a- b- d- a+ c-a a+ b+ c+ a- b- c- a+ c- a- d- d+

a+ b+ c+ a- b- c- a+ c- a- d- d+ ab cd ER(d+) ER(d-)

ab cd a+ b+ c+ a- b- c- a+ c- a- d- d+ Complex gate

ASYNC Tutorial on Petrify Method and Tool37 Implementation with C elements C R S z  S+  z+  S-  R+  z-  R-  S (set) and R (reset) must be mutually exclusive S must cover ER(z+) and must not intersect ER(z-)  QR(z-) R must cover ER(z-) and must not intersect ER(z+)  QR(z+)

ab cd a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d

a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d but...

a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d Assume that R=ac has an unbounded delay Starting from state 0000 (R=1 and S=0): a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; R+ disabled (potential glitch)

ab cd a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d Monotonic covers

ASYNC Tutorial on Petrify Method and Tool42 C-based implementations C S R d C d a b c a b c d weak a c d generalized C elements (gC) weak

ASYNC Tutorial on Petrify Method and Tool43 Speed-independent implementations Implementation conditions –Consistency –Complete state coding –Persistency Circuit architectures –Complex (hazard-free) gates –C elements with monotonic covers –...

ASYNC Tutorial on Petrify Method and Tool44 Synthesis exercise y- z-w- y+x+ z+ x- w y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ Derive circuits for signals x and z (complex gates and monotonic covers)

ASYNC Tutorial on Petrify Method and Tool45 Synthesis exercise y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ wx yz Signal x

ASYNC Tutorial on Petrify Method and Tool46 Synthesis exercise y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ wx yz Signal z

ASYNC Tutorial on Petrify Method and Tool47 A simple filter: specification y := 0; loop x := READ (IN); WRITE (OUT, (x+y)/2); y := x; end loop R in A in A out R out IN OUT filter

ASYNC Tutorial on Petrify Method and Tool48 A simple filter: block diagram xy + control R in A in R out A out RxRx AxAx RyRy AyAy RaRa AaAa IN OUT x and y are level-sensitive latches (transparent when R=1) + is a bundled-data adder (matched delay between R a and A a ) R in indicates the validity of IN After A in + the environment is allowed to change IN (R out,A out ) control a level-sensitive latch at the output

ASYNC Tutorial on Petrify Method and Tool49 A simple filter: control spec. xy + control R in A in R out A out RxRx AxAx RyRy AyAy RaRa AaAa IN OUT R in + A in + R in - A in - Rx+Rx+ Ax+Ax+ Rx-Rx- Ax-Ax- Ry+Ry+ Ay+Ay+ Ry-Ry- Ay-Ay- Ra+Ra+ Aa+Aa+ Ra-Ra- Aa-Aa- R out + A out + R out - A out -

ASYNC Tutorial on Petrify Method and Tool50 A simple filter: control impl. R in + A in + R in - A in - Rx+Rx+ Ax+Ax+ Rx-Rx- Ax-Ax- Ry+Ry+ Ay+Ay+ Ry-Ry- Ay-Ay- Ra+Ra+ Aa+Aa+ Ra-Ra- Aa-Aa- R out + A out + R out - A out - C R in A in RxRx AxAx RyRy AyAy AaAa RaRa A out R out

ASYNC Tutorial on Petrify Method and Tool51 Control: observable behavior Rx+Rx+ R in + Ax+Ax+Ra+Ra+Aa+Aa+R out +A out +z+R out -A out -Ry+Ry+ Ry-Ry- Ay+Ay+ Rx-Rx-Ax-Ax- Ay-Ay- A in - A in + Ra-Ra- R in - Aa-Aa- z- C R in A in RxRx AxAx RyRy AyAy AaAa RaRa A out R out z

ASYNC Tutorial on Petrify Method and Tool52 Following slides borrowed from Ran Ginosar, Technion (VLSI Architectures course) with thanks

ASYNC Tutorial on Petrify Method and Tool53 Generalized C Element From Ran Ginosar’s course

ASYNC Tutorial on Petrify Method and Tool54 STG Rules Any STG: –Input free-choice—Only inputs may control the choice) –Bounded—Maximum k (given bound) token per place –Liveness—every signal transition can be activated STG for Speed Independent circuits: –Consistent state assignment—Signals strictly alternate between + and – –Persistency—Excited non-input signals must fire, namely they cannot be disabled by another transition Synthesizable STG: –Complete state coding—Different markings must represent different states

ASYNC Tutorial on Petrify Method and Tool55 We use the following circuit to explain STG rules: req ack REQ ACK

ASYNC Tutorial on Petrify Method and Tool56 1-Bounded (Safety) STG is safe if no place or arc can ever contain more than one token Often caused by one-sided dependency STG is not safe: If left cycle goes fast and right cycle lags, then arc ack+  REQ+ accumulates tokens. ( REQ+ depends on both ack+ and ACK- ) Possible solution: stop left cycle by right cycle REQ+ACK+ REQ- ACK- req+ack+ req- ack-

ASYNC Tutorial on Petrify Method and Tool57 Liveness STG is live if from every reachable marking, every transition can eventually be fired The STG is not live: Transitions reset, reset_ok cannot be repeated. But non-liveness is useful for initialization reset_ok-reset-req+ack+ req- ack-

ASYNC Tutorial on Petrify Method and Tool58 Consistent state assignment The following subgraph of STG makes no sense: a+ a-

ASYNC Tutorial on Petrify Method and Tool59 Persistency STG is persistent if for all non-input transitions once enabled the transition cannot be disabled by another transitions. Non-persistency may be caused by arbitration or dynamic conflict relations – STG must have places STG is not persistent: there is a place between req+ and  ack+ in which a token is needed in order to fire REQ+. So there is some sort of nondeterminism – either REQ+ manages to fire before ack+ or not Possible solution: introduce proper dependence of the left cylce on the right one (e.g., an arc from req+ to REQ+, and from REQ+ to ack+) REQ+ACK+ REQ- ACK- req+ ack+req- ack-

60 Complete State Coding STG has a complete state coding if no two different markings have identical values for all signals. REQ+ACK+ REQ- ACK- ack-req+ ack+ req req,ack,REQ,ACK: cd\ab Disaster!

ASYNC Tutorial on Petrify Method and Tool61 Complete State Coding Possible solution: Add an internal state variable x-x+ req,ack,REQ,ACK,x: REQ+ACK+ REQ- ACK- ack-req+ ack+ req

ASYNC Tutorial on Petrify Method and Tool62 A faster STG? Does it need an extra variable? ack- req+ ack+ req- ACK- REQ+ ACK+ REQ-

ASYNC Tutorial on Petrify Method and Tool63 STG specification in.astg format.model simple_buffer.inputs r A.outputs a R.graph # left handshake (r,a) r+ a+ a+ r- r- a- a- r+ # right handshake (R,A) R+ A+ A+ R- R- A- A- R+ # interaction between handshakes r+ R+ A+ a-.marking{ }.end

ASYNC Tutorial on Petrify Method and Tool64 Drawn by draw_astg

65 The SG req,ack,REQ,ACK: 0000 r a+ R r R a+ A A a+r R+ a- A r a- R R a+ R r a- R- A A a+ A r- a- A r r+ R- A a+ R a+ A r- R r- A- a-

66 The SG req,ack,REQ,ACK: 0000 r a+ R r R a+ A A a+r R+ a- A r a- R R a+ R r a- R- A A a+ A r- a- A r r+ R- A a+ R a+ A r- R r- A- a- R+ CSC-conflict states are highlighted

ASYNC Tutorial on Petrify Method and Tool67 Drawn by write_sg & draw_astg

ASYNC Tutorial on Petrify Method and Tool68 Extra states inserted by petrify

ASYNC Tutorial on Petrify Method and Tool69 Rearranged STG ack- req+ ack+ req- c1- c1+ c0- ACK- REQ+ ACK+ REQ- c2- c2+ c0+ Initial Internal State: c0=c1=c2=1

ASYNC Tutorial on Petrify Method and Tool70 The new State Graph…

ASYNC Tutorial on Petrify Method and Tool71 The Synthesized Complex Gates Circuit INORDER = r A a R csc0 csc1 csc2; OUTORDER = [a] [R] [csc0] [csc1] [csc2]; [a] = a (csc2 + csc0) + csc1'; [R] = csc2 (csc0 (a + r) + R); [csc0] = csc0 (csc1' + a') + R' csc2; [csc1] = r' (csc0 + csc1); [csc2] = A' (csc0' (csc1' + a') + csc2);

ASYNC Tutorial on Petrify Method and Tool72 Technology Mapping INORDER = r A a R csc0 csc1 csc2; OUTORDER = [a] [R] [csc0] [csc1] [csc2]; [0] = R'; # gate inv:combinational [1] = [0]' A' + csc2'; # gate oai12:combinational [a] = a csc0' + [1]; # gate sr_nor:asynch [3] = csc1'; # gate inv:combinational [4] = csc0' csc2' [3]'; # gate nor3:combinational [5] = [4]' (csc1' + R'); # gate aoi12:combinational [R] = [5]'; # gate inv:combinational [7] = (csc2' + a') (csc0' + A');# gate aoi22:combinational [8] = csc0'; # gate inv:combinational [csc0] = [8]' csc1' + [7]'; # gate oai12:combinational [csc1] = A' (csc0 + csc1); # gate rs_nor:asynch [11] = R'; # gate inv:combinational [12] = csc0' ([11]' + csc1'); # gate aoi12:combinational [csc2] = [12] (r' + csc2) + r' csc2; # gate c_element1:asynch

ASYNC Tutorial on Petrify Method and Tool73 The Synthesized Gen-C Circuit INORDER = r A a R csc0 csc1 csc2; OUTORDER = [a] [R] [csc0] [csc1] [csc2]; [0] = csc0' csc1 (R' + A); [1] = csc0 csc2 (a + r); [2] = csc2' A; [R] = R [2]' + [1]; # mappable onto gC [4] = a csc1 csc2'; [csc0] = csc0 [4]' + csc2; # mappable onto gC [6] = r' csc0; [csc1] = csc1 r' + [6]; # mappable onto gC [8] = A' csc0' (csc1' + a'); [csc2] = csc2 R' + [8]; # mappable onto gC [a] = a [0]' + csc1'; # mappable onto gC

ASYNC Tutorial on Petrify Method and Tool74 Petrify Environment STG EQN draw_astg ps write_sg SG lib petrify

ASYNC Tutorial on Petrify Method and Tool75 Petrify Unix (Linux) command line tool petrify –h for help (flags etc.) petrify –cg for complex gates petrify –gc for generalized C-elements petrify –tm for tech mapping draw_astg to draw write_sg to create state graphs Documented on line, including tutorial

ASYNC Tutorial on Petrify Method and Tool76 References See the attached Practical Exercise manual for various design examples using Petrify commands Additional references: –Petrify and all documentation can be downloaded from: –J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces, Springer, Berlin, 2002, ISBN