1 Design of a Sequence Detector (14.1) Seq. ends in 101 --> Z=1 (no reset) Otherwise--> Z=0 Typical input/output sequence Partial Soln. (Mealy Network):

Slides:



Advertisements
Similar presentations
©2004 Brooks/Cole FIGURES FOR CHAPTER 14 DERIVATION OF STATE GRAPHS AND TABLES Click the mouse to move to the next page. Use the ESC key to exit this chapter.
Advertisements

STATE DIAGRAM AND STATE TABLES
Sequential Circuits Storage elements
State-machine structure (Mealy)
State Machine Design Procedure
L7 – Derivation of State Graphs and Tables – Moore Machines.
Analysis of Clocked Sequential Circuits
Sequential Circuit Analysis & Design Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Dr. Aiman H. El-Maleh.
Digital Logic Design Lecture 27.
A Sequential Parity Checker
Nonlinear & Neural Networks LAB. CHAPTER 13 Analysis of Clocked Sequential Circuit 13.1 A Sequential Parity Checker 13.2 Analysis by Signal Tracing 13.3.
Unit 13 Analysis of Clocked Sequential Circuits Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information.
UNIT 14 DERIVATION OF STATE GRAPHS AND TABLES Spring 2011.
Sequential Circuit Design
ECE 331 – Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #20) The slides included herein were taken from the.
ECE 331 – Digital System Design
Sequential Circuits and Finite State Machines Prof. Sin-Min Lee
1 State Reduction: Row Matching Example 1, Section 14.3 is reworked, setting up enough states to remember the first three bits of every possible input.
Sequential Circuit Design
Overview Sequential Circuit Design Specification Formulation
1 Assumptions: (i) Network A can only generate sequences X=100 and X = 110. (ii) Network B produces output Z=1 when it receives X=110 and output Z=0 for.
9/15/09 - L22 Sequential Circuit Design Copyright Joanne DeGroat, ECE, OSU1 Sequential Circuit Design Creating a sequential circuit to address a.
Sequential circuit design
Digital Computer Design Fundamental
L5 – Sequential Circuit Design
Chapter 5 - Part Sequential Circuit Design Design Procedure  Specification  Formulation - Obtain a state diagram or state table  State Assignment.
Rabie A. Ramadan Lecture 3
State Machines.
Unit 14 Derivation of State Graphs
Introduction to Sequential Circuit By : Pn Siti Nor Diana Ismail CHAPTER 5.
L6 – Derivation of State Graphs and Tables. State Graphs and Tables  Problem Statement translation To State Graphs To State Tables  Ref: text : Unit.
Important Components, Blocks and Methodologies. To remember 1.EXORS 2.Counters and Generalized Counters 3.State Machines (Moore, Mealy, Rabin-Scott) 4.Controllers.
Introduction to State Machine
General model of a sequential network.
DLD Lecture 26 Finite State Machine Design Procedure.
1 Recap lecture 22 Applications of complementing and incrementing machines, Equivalent machines, Moore equivalent to Mealy, proof, example, Mealy equivalent.
DESIGN OF SEQUENTIAL CIRCUITS by Dr. Amin Danial Asham.
CEC 220 Digital Circuit Design Timing Analysis of State Machines
1 State Reduction Goal: reduce the number of states while keeping the external input-output requirements unchanged. State reduction example: a: input 0.
1Sequential circuit design Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA by Erol Sahin and Ruken Cakici.
CEC 220 Digital Circuit Design Mealy and Moore State Machines Friday, March 27 CEC 220 Digital Circuit Design Slide 1 of 16.
Lecture # 15. Mealy machine A Mealy machine consists of the following 1. A finite set of states q 0, q 1, q 2, … where q 0 is the initial state. 2. An.
CHAPTER 7 DESIGNING SEQUENTIAL SYSTEMS. CE6. A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive.
Synchronous Counter Design
Lecture 22: Finite State Machines with Output. Moore Machine - A Moore machine is a 6-tuple (Q, , , , q 0,  ) where, (1) Q is a finite set of states.
Sequential Circuit Design 05 Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.
State Diagrams Tuesday, 12 September State diagram Graphical representation of a state table. –Provides the same information as a state table. –A.
SLIDES FOR CHAPTER 15 REDUCTION OF STATE TABLES STATE ASSIGNMENT
L5 – Sequential Circuit Design
Lecture 13 Derivation of State Graphs and Tables
CS 352 Introduction to Logic Design
Lecture 12 Analysis of Clocked Sequential Network
Analysis of Clocked Sequential Circuit
SLIDES FOR CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
CS 352 Introduction to Logic Design
Asynchronous Inputs of a Flip-Flop
CPE/EE 422/522 Advanced Logic Design L03
State Reduction and State Assignment
KU College of Engineering Elec 204: Digital Systems Design
Sequential circuit design
Sequential circuit design
ECE 434 Advanced Digital System L05
ECE434a Advanced Digital Systems L06
Sequential circuit design
KU College of Engineering Elec 204: Digital Systems Design
CHAPTER 15 REDUCTION OF STATE TABLES STATE ASSIGNMENT
Sequential Design Example
Lecture 20 State minimization via row matching.
EGR 2131 Unit 12 Synchronous Sequential Circuits
Chapter5: Synchronous Sequential Logic – Part 3
Presentation transcript:

1 Design of a Sequence Detector (14.1) Seq. ends in > Z=1 (no reset) Otherwise--> Z=0 Typical input/output sequence Partial Soln. (Mealy Network): Initially start in state S 0 - the reset state 0 received - stay in S 0 1 received go to a new state S 1

2 Design of a Sequence Detector (14.1) Seq. ends in > Z=1 (no reset) otherwise--> Z=0 Partial Soln.: 0 received in S 1 - go to a new state S 2 1 received in S 2 seq. (101) rec’d (Z=1) -cannot go back to S 0 (no reset) -go back to state S 1 since last 1 could be part of a new seq. Final State Graph: 1 received in S 1 - stay in S 1 (seq. restarted) 0 received in S 2 seq. (00) rec’d -must reset to S 0

3 Design of a Sequence Detector (14.1) Convert State Graph to State Table: Represent the three states with two FF’s A and B to obtain the transition table. Seq. ends in > Z=1 (no reset) otherwise--> Z=0

4 Design of a Sequence Detector (14.1) Plot next state and Z maps from transition table

5 Design of a Sequence Detector (14.1) From the next state and Z maps we obtained: A + = X’B, B + = X, Z = XA If D FF’s are used D A = A +, D B = B + which leads to the network:

6 Design of a Sequence Detector (14.1 Moore) Seq. ends in > Z=1 (no reset) otherwise--> Z=0 For the Moore Network: When a 1 is rec’d to complete seq. (101) -must have Z=1 so must create a new state S 3 with output Z=1 Note the seq. 100 resets the network to S 0 Final State Graph

7 Design of a Sequence Detector (14.1 Moore) Convert State Graph to State Table: Represent the four states with two FF’s A and B to obtain the transition table. FF input eqns. can be derived as was done for Mealy network.

8 Seq. ends in 010 or > Z=1 Otherwise --> Z=0 Mealy Sequential Network (14.2) Partial State Graph -gives Z=1 for seq. 010

9 Seq. ends in 010 or > Z=1 Otherwise --> Z=0 Mealy Sequential Network (14.2) Partial State Graph -additional states for seq. (1001)

10 Seq. ends in 010 or > Z=1 Otherwise --> Z=0 Mealy Sequential Network (14.2) Final State Graph -takes into account all other input sequences

11 Z=1 if total no. of 1’s received is odd and at least two consecutive 0’s rec’d Moore Sequential Network (14.2)

12 Z=1 if total no. of 1’s received is odd and at least two consecutive 0’s rec’d Moore Sequential Network (14.2)

13 Guidelines for Construction of State Graphs

14 Final graph includes other seq. 1111

15 Soln.: The repeating part of the sequence is generated using a loop. (A blank space above the slash indicates that the network has no other Input than the clock.)

16 States are based on the previous input pair. Don’t need separate states for 00, 11 since neither input starts a seq. which leads to an output change. However, for each previous Input, the output could be 0 or 1, so we need six states.

17 Example 3 cont’d We can set up the state table shown below. e.g. S 4 row: If 00 rec’d the input seq. has been 10,00 so output does not change and we go to S 0. If 01 rec’d the input seq. has been 10,01 so output changes to 1 and we go to S 3. If 11 rec’d the input seq. has been 10,11 so output changes to 1 and we go to S 1. If 10 rec’d the input seq. has been 10,10 so output does not change and we stay in S 4. 01,11 --> 0 10,11 --> 1 10,01 --> change

18 Example 3 cont’d 01,11 --> 0 10,11 --> 1 10,01 --> change

19 Coding schemes for serial data transmission –NRZ: nonreturn-to-zero –NRZI: nonreturn-to-zero-inverted 0 - same as the previous bit; 1 - complement of the previous bit –RZ: return-to-zero 0 – 0 for full bit time; 1 – 1 for the first half, 0 for the second half –Manchester A Converter for Serial Data Transmission: NRZ-to-Manchester

20 Moore Network for NRZ-to-Manchester

21 Moore Network for NRZ-to-Manchester

22 Mealy Network for NRZ-to-Manchester