26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 1 OPTIMIZATION OF CURRENT MODE MULTIVALUED LOGIC CIRCUITS Avni MORG Ü L and Fatma SARICA Boğazi ç i University Electrical&Electronics Engineering Department Istanbul, TURKEY Presented By: Avni Morg ü l

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 2 MVL: Multi-Valued Logic fills the gap between digital&analog More than two logic level (r>2) Logic functions may be implemented –Using less number of transistor (smaller chip area) –Using less number of interconnections –Faster Disadvantages: –Static power dissipation –Lower noise margin Applications: –Faster signal processor circuits with reduced chip area and less interconnections.

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 3 Definitions In the current mode implementation each logic level is represented by a current level I j = j  I b, The base current I b corresponds to one step of discrete current variation. A logic level l corresponds to an interval of cont. variable, y y  l : {y|(j-0.5)I b  y < (j+0.5)I b } (j+0.5)I b (j-0.5)I b y  IjIj discrete out jI b l continuous input IbIb Number of discrete values: radix ( r )

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 4 Implementation By using current-mode CMOS circuit i. The basic circuit Elements znzn N z1z :k x n-type current mirror Multiplying and re-directing a current x 1:k z1z1 znzn MdMd MmMm zn zn xkx N z1 z1 P the symbol the circuit

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 5 Inverter r- 1 1:1 z x MdMd MmMm z r- 1 x N x 0 Slope = -1

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 6 min(x,y) gate z x y y Slope = 1 y N2 N3 x N1 z N4 y xin vddmin vssmin innext yin 35.5µm×19µm IC Layout y 1:1 x N N z x y y P y N min(x,y) = x  y = x y

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 7 Threshold circuit upper threshold, th u : z u z u (a,b,c) th u+ b a c a c  I b z u (a,b,c) c N4 a b N1 N2 N3 lower threshold, th l : z l (a,b,c) th l+ b a c z l (a,b,c) c N4 b a N1 N2 N3 a c  I b z l

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 8 Comparison with binary FA MVL- radix-8 adder: (12 trans.) 87µm×24µm 3-bit binary-RCA: (84 trans.) 160µm×85µm

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 9 Level Variation Problem The level of the gate output signals may vary from the predefined discrete levels due to; –The non-idealities in the circuit (Mismatch) –Variation of input signals –Noise

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 10 Statistical Mismatch Analysis Mismatch models of MOS transistors include two terms: –a size dependent and –a distance dependent term In this study we will concentrate on size dependent term and we assume that variations in W/L ratios will be the dominating term The drain current may be expressed as follows: where

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 11 Statistical Mismatch Analysis The variance in z =I out due to the dimension mismatches in the transistors may be defined as Calculated output current deviationSimulated output current deviation

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 12 LEVEL RESTORATION Unlike CMOS binary logic circuits, CMOS MVL circuits are not self restored. This causes noise margin to be critical after a number of stages. A level restorer circuit must be used after a certain number of stages to recover the signal

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 13 Level Restoration The maximum number of identical structures that can be cascaded, without loosing a predefined logic level at the output, is limited. Maximum radix of a given MVL implementation depends on logic level degradations of basic gates, such as min gate,  min. The allowable logic level degradation or a standard deviation for each m -input gate with radix r can be determined by

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 14 Level Restoration It is necessary to restore the deviated levels after a certain number of cascaded gates Process (W/L) n ; (W/L) p %σ  z/z z=min(x,y) %σ  z/z z=max(x,y) 1.75/1; 5.5/ /1.5; 8/ Gate-1Gate-2Gate-3RestorerGate-4 inout

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 15 Statistical Analysis Deviation of the output current from the nominal value, for k cascaded stages z, Az, A x,  A y= 30  A k =1 k =4 k =8

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 16 8-Level Restorer Circuit

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 17 Simulations Simulation result (100 runs) for 6 stages of min circuits with large transistors Worst case of 100 Monte Carlo simulations for 3 cascaded stages of min circuits with small transistors variation

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 18 Simulations Spice simulations indicate that maximum allowable number of cascaded min circuits using the dimensions of W/L=40/20µm, is 6 The output deviation reaches the critical noise margin (1/2 I 0 ) after the 6th stage for large transistors, and it is not possible to add one more stage The max. number of stages for small transistors ( W/L=20/10µm) is only 3. A restorer circuit is necessary after these three stages. Restoration circuit corrects the deviations at the output current.

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 19 COMPARISON Qestion: ‘Which one of the following situations is advantageous in the area consumption and noise margin point of view: –using a restorer circuit or, –increasing the dimensions of the active elements?” The min circuit is selected as a model circuit. Dimensions of the model circuit are chosen such that the output current of the specified number of the cascaded blocks remain within the critical noise margin. Same circuit is built by using minimum size transistors, and a restoration circuit. Total areas are calculated for both circuit and compared.

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 20 COMPARISON Layouts of the two circuits are drawn using the Magic Layout program and total areas of the circuits are calculated. It is found that using a level restoration circuit reduces the total area consumption nearly 25%, compared to large sized transistors. Six stages with W/L=40/20µm, Total area=497µm×271µm Six stages with W/L=20/10µm, plus the restorer circuit. Total area=439µm×226µm

26-28 Apr. 2006A. Morgül – GAP’2006, Şanlıurfa, TURKEY 21 CONCLUSION The number of cascaded stages is limited in the MVL implementation due to the mismatches and smaller noise margins compared to binary logic. The number of cascaded stages may be increased either by increasing the sizes of transistors or by adding a restorer circuit after a certain number of stages. We compare these two solutions and found that the solution with a restoration circuit saves about 25% in the total chip area.