ISPD 2000, San DiegoApr 10, 2000 --1-- Requirements for Models of Achievable Routing Andrew B. Kahng, UCLA Stefanus Mantik, UCLA Dirk Stroobandt, Ghent.

Slides:

Advertisements

Similar presentations

-1- VLSI CAD Laboratory, UC San Diego Post-Routing BEOL Layout Optimization for Improved Time- Dependent Dielectric Breakdown (TDDB) Reliability Tuck-Boon.

Advertisements

Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.

Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.

Hsi-An Chien Ting-Chi Wang Redundant-Via-Aware ECO Routing ASPDAC2014.

BSPlace: A BLE Swapping technique for placement Minsik Hong George Hwang Hemayamini Kurra Minjun Seo 1.

Reap What You Sow: Spare Cells for Post-Silicon Metal Fix Kai-hui Chang, Igor L. Markov and Valeria Bertacco ISPD’08, Pages

Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.

Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.

SLIP 2008, Newcastle Revisiting Fidelity: A Case of Elmore-based Y-routing Trees Tuhina Samanta*, Prasun Ghosal*, Hafizur Rahaman* and Parthasarathi Dasgupta†

Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim

DARPA Assessing Parameter and Model Sensitivities of Cycle-Time Predictions Using GTX u Abstract The GTX (GSRC Technology Extrapolation) system serves.

Toward Better Wireload Models in the Presence of Obstacles* Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu and Dirk Stroobandt† UC San Diego CSE Dept. †Ghent.

Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength Estimator Andrew B. KahngSherief Reda VLSI CAD Laboratory.

On the Relevance of Wire Load Models Kenneth D. Boese, Cadence Design Systems, San Jose Andrew B. Kahng, UCSD CSE and ECE Depts., La Jolla Stefanus Mantik,

Architectural-Level Prediction of Interconnect Wirelength and Fanout Kwangok Jeong, Andrew B. Kahng and Kambiz Samadi UCSD VLSI CAD Laboratory

Study of Floating Fill Impact on Interconnect Capacitance Andrew B. Kahng Kambiz Samadi Puneet Sharma CSE and ECE Departments University of California,

On Modeling and Sensitivity of Via Count in SOC Physical Implementation Kwangok Jeong Andrew B. Kahng.

Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction The Road to Future Computer.

Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction The Road to Future Computer.

1 A Tale of Two Nets: Studies in Wirelength Progression in Physical Design Andrew B. Kahng Sherief Reda CSE Department University of CA, San Diego.

On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.

University of Toronto Pre-Layout Estimation of Individual Wire Lengths Srinivas Bodapati (Univ. of Illinois) Farid N. Najm (Univ. of Toronto)

Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu (Kevin) Cao 1, Chenming Hu 1, Xuejue Huang 1, Andrew.

Can Recursive Bisection Alone Produce Routable Placements? Andrew E. Caldwell Andrew B. Kahng Igor L. Markov Supported by Cadence.

Accurate Pseudo-Constructive Wirelength and Congestion Estimation Andrew B. Kahng, UCSD CSE and ECE Depts., La Jolla Xu Xu, UCSD CSE Dept., La Jolla Supported.

Interconnect Implications of Growth-Based Structural Models for VLSI Circuits* Chung-Kuan Cheng, Andrew B. Kahng and Bao Liu UC San Diego CSE Dept.

SLIP 2000April 9, Wiring Layer Assignments with Consistent Stage Delays Andrew B. Kahng (UCLA) Dirk Stroobandt (Ghent University) Supported.

Cost-Based Tradeoff Analysis of Standard Cell Designs Peng Li Pranab K. Nag Wojciech Maly Electrical and Computer Engineering Carnegie Mellon University.

UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.

7/13/ EE4271 VLSI Design VLSI Routing. 2 7/13/2015 Routing Problem Routing to reduce the area.

Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar.

MGR: Multi-Level Global Router Yue Xu and Chris Chu Department of Electrical and Computer Engineering Iowa State University ICCAD

CRISP: Congestion Reduction by Iterated Spreading during Placement Jarrod A. Roy†‡, Natarajan Viswanathan‡, Gi-Joon Nam‡, Charles J. Alpert‡ and Igor L.

Global Routing.

Are classical design flows suitable below 0.18  ? ISPD 2001 NEC Electronics Inc. WR0999.ppt-1 Wolfgang Roethig Senior Engineering Manager EDA R&D Group.

TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.

Archer: A History-Driven Global Routing Algorithm Mustafa Ozdal Intel Corporation Martin D. F. Wong Univ. of Illinois at Urbana-Champaign Mustafa Ozdal.

Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement Jarrod A. Roy, James F. Lu and Igor L. Markov University of Michigan Ann.

Improved Cut Sequences for Partitioning Based Placement Mehmet Can YILDIZ and Patrick H. Madden State University of New York at BinghamtonComputer Science.

Kwangsoo Han‡, Andrew B. Kahng‡† and Hyein Lee‡

"A probabilistic approach to clock cycle prediction" A probabilistic approach to clock cycle prediction J. Dambre, D. Stroobandt and J. Van Campenhout.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing © KLMH Lienig 1 What Makes a Design Difficult to Route Charles.

GLARE: Global and Local Wiring Aware Routability Evaluation Yaoguang Wei1, Cliff Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi Reddy,

Impact of Interconnect Architecture on VPSAs (Via-Programmed Structured ASICs) Usman Ahmed Guy Lemieux Steve Wilton System-on-Chip Lab University of British.

ARCHER:A HISTORY-DRIVEN GLOBAL ROUTING ALGORITHM Muhammet Mustafa Ozdal, Martin D. F. Wong ICCAD ’ 07.

Congestion Estimation and Localization in FPGAs: A Visual Tool for Interconnect Prediction David Yeager Darius Chiu Guy Lemieux The University of British.

International Workshop on System-Level Interconnection Prediction, Sonoma County, CA March 2001ER UCLA UCLA 1 Wirelength Estimation based on Rent Exponents.

ILP-Based Inter-Die Routing for 3D ICs Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu Department of Electrical Engineering, National.

"Fast estimation of the partitioning Rent characteristic" Fast estimation of the partitioning Rent characteristic using a recursive partitioning model.

System in Package and Chip-Package-Board Co-Design

Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction Rent’s Rule and Wire Length.

Pre-layout prediction of interconnect manufacturability Phillip Christie University of Delaware USA Jose Pineda de Gyvez Philips Research Laboratories.

International Symposium on Physical Design San Diego, CA April 2002ER UCLA UCLA 1 Routability Driven White Space Allocation for Fixed-Die Standard-Cell.

Dirk Stroobandt Ghent University Electronics and Information Systems Department A New Design Methodology Based on System-Level Interconnect Prediction.

An Exact Algorithm for Difficult Detailed Routing Problems Kolja Sulimma Wolfgang Kunz J. W.-Goethe Universität Frankfurt.

Hypergraph Partitioning With Fixed Vertices Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov UCLA Computer Science Department

Interconnect Characteristics of 2.5-D System Integration Scheme Yangdong (Steven) Deng & Wojciech P. Maly

Dept. of Electronics Engineering & Institute of Electronics National Chiao Tung University Hsinchu, Taiwan ISPD’16 Generating Routing-Driven Power Distribution.

Dirk Stroobandt Ghent University Electronics and Information Systems Department Multi-terminal Nets do Change Conventional Wire Length Distribution Models.

EE4271 VLSI Design VLSI Channel Routing.

Prediction of Interconnect Net-Degree Distribution Based on Rent’s Rule Tao Wan and Malgorzata Chrzanowska- Jeske Department of Electrical and Computer.

Slide 1 SLIP 2004 Payman Zarkesh-Ha, Ken Doniger, William Loh, and Peter Bendix LSI Logic Corporation Interconnect Modeling Group February 14, 2004 Prediction.

The Interconnect Delay Bottleneck.

On the Relevance of Wire Load Models

Revisiting and Bounding the Benefit From 3D Integration

Multilevel Full-Chip Routing for the X-Based Architecture

Sheqin Dong, Song Chen, Xianlong Hong EDA Lab., Tsinghua Univ. Beijing

Interconnect Architecture

Puneet Gupta1 , Andrew B. Kahng1 , Youngmin Kim2, Dennis Sylvester2

EE4271 VLSI Design, Fall 2016 VLSI Channel Routing.

Presentation transcript:

ISPD 2000, San DiegoApr 10, Requirements for Models of Achievable Routing Andrew B. Kahng, UCLA Stefanus Mantik, UCLA Dirk Stroobandt, Ghent Univ. Supported by Cadence Design Systems, Inc. and the MARCO Gigascale Silicon Research Center

ISPD 2000, San DiegoApr 10, Outline Models of achievable routing Review of existing models Validation of models through experiments! Experimental analysis of assumptions Future model requirements Conclusions

ISPD 2000, San DiegoApr 10, –wirelength estimation models (Donath, …) –actual placement information Models of achievable routing Required versus available resources

ISPD 2000, San DiegoApr 10, Models of achievable routing Required versus available resources limited by routing efficiency factor  r

ISPD 2000, San DiegoApr 10, Models of achievable routing Required versus available resources limited by power/ground (signal net fraction s i )

ISPD 2000, San DiegoApr 10, Models of achievable routing Required versus available resources limited by via impact factor v i (ripple effect) utilization factor U i (available / supplied area)

ISPD 2000, San DiegoApr 10, Use of achievable routing models Optimizing interconnect process parameters for future designs (number of layers, wire width and pitch per layer,...) With given layer characteristics: predict the number of layers needed If number of layers fixed: oracle “(not) routable!” (SUSPENS, GENESYS, RIPE, BACPAC, GTX) Supplying objectives that guide layout tools to promising solutions (wire planning)

ISPD 2000, San DiegoApr 10, Validation is key Models must be accurate, must support empirical verification and calibration No existing model is validated with real place-and-route data Our work concentrates on validation: –understanding reasons for validation gap –processes for model validation –improvements needed in future models

ISPD 2000, San DiegoApr 10, Review of existing models Sai-Halasz [Proc. IEEE, 1995] –power/ground: s i 20% –routing efficiency:  r = 40% –via impact: each layer blocks 15% on layers below with same pitch –model is widely used –model is rather pessimistic

ISPD 2000, San DiegoApr 10, Review of existing models (cont.) Chong and Brayton [SLIP, 1999] –layer assignment model layer pairs form tiers (H and V) wires are routed on 1 tier shorter wires on lower tiers –available resources model constant routing efficiency for all layers:  r = 65% via impact factor v i based on actual via area –each wire uses 2 via stacks (block wires on lower layers) –total number of wires per layer (thus vias) defined by layer assignment model H H V V } } tier

ISPD 2000, San DiegoApr 10, Review of existing models (cont.) Chen et al. [private communication, 1999] –layer assignment model similar to Chong’s –available resources model constant routing efficiency (40% <  r < 66%) via impact model –terminal vias and turn vias –each wire uses 2 via stacks –number of terminal vias defined by layer assignment model –sparse via model = Chong –dense via model: give up 1 track every X tracks –results in via impact proportional to sqrt(Chong’s impact factor) H H V V } } tier tracks

ISPD 2000, San DiegoApr 10, Model validation Models can be validated only by testing against comparable experimental results –none of reviewed models was validated –even simple comparison: huge differences Via fill rate (%) Utilization factor/layer (%) Sai-Halasz (M4) Sai-Halasz (M1) Chong Chen Sai-Halasz (M3) Sai-Halasz (M2)

ISPD 2000, San DiegoApr 10, Model validation (cont.) Experimental validation –Typical industry standard-cell block design cells, 1999, 5 layers Cadence placement and gridded routing tools same pitch (1  m) for all layers via size.62  m all pins for cells are on M1 Experimental validation –ensure congested design Via fill rate (%) Utilization factor (%) Sai-Halasz (M4) Sai-Halasz (M1) Chong Chen Sai-Halasz (M3) Sai-Halasz (M2) Exp M Exp M4 Exp M3

ISPD 2000, San DiegoApr 10, Model validation (cont.) Experimental validation –adding virtual vias on M3 and M4 (effect of wires on virtual upper layers) Exp M4 Exp M3 Via fill rate (%) Utilization factor (%) Sai-Halasz (M4) Sai-Halasz (M1) Chong Chen Sai-Halasz (M3) Sai-Halasz (M2) Exp M

ISPD 2000, San DiegoApr 10, Model validation (cont.) Predictions for future designs –number of layers >>, die size >> –via impact severely underestimated –predicted limits on number of layers too high Via fill rate (%) Utilization factor (%) Chong Chen M4 M

ISPD 2000, San DiegoApr 10, Model validation (cont.) Predictions for future designs LayerChongChenExperiment M M M M4000 Total Layers needed224 Number of terminal vias

ISPD 2000, San DiegoApr 10, Outline Models of achievable routing Review of existing models Validation of models through experiments! Experimental analysis of assumptions Future model requirements Conclusions

ISPD 2000, San DiegoApr 10, Routing efficiency Constant over all layers? Via fill rate (%) Utilization factor (%) Chong Chen M4 M

ISPD 2000, San DiegoApr 10, Routing efficiency Are we measuring routing efficiency or inefficiency? –thought experiment given placement of given netlist route with very good router, measure U i route again with very bad router, measure U i –which one has better routing efficiency? –which one has higher utilization factor? –Give credit for completing nets, not for using metal (use Steiner length instead of actual length for U i )!

ISPD 2000, San DiegoApr 10, Layer assignment assumptions shorter wires on lower tiers / wires on 1 tier Actual Length (%) Actual Number of Layers Steiner Length (  m)

ISPD 2000, San DiegoApr 10, Real Wiring Effects Cascade/ripple effect Effect of vias depends on wire length Proposal: l+1 intersections

ISPD 2000, San DiegoApr 10, Real Wiring Effects (cont.) A simple proposal –probability wire is not blocked: –via impact factor: Via fill rate (%) Utilization factor (%) Chong Chen M4 M Model M3Model M4

ISPD 2000, San DiegoApr 10, Conclusion Better/more accurate models needed –understanding routing efficiency –layer assignment model allows >1 tier/wire –via impact based on real wiring effects wirelength on layer is important cascade/ripple effect Experimental verification of models a must! There is a lot of work yet to be done

ISPD 2000, San DiegoApr 10, Constant via impact factor Utilization factor constant? LayerSai-HalaszU i /U i+1 M1/M M2/M M3/M M3/M4 Utilization factor ratio Via fill rate (%)