1 At-Speed BISR Analyzer for Embedded Word-Oriented Memories Xiaogang Du Sudhakar M. Reddy ECE Department University of Iowa 17 th International Conference on VLSI Design (VLSID2004) Wu-Tung Cheng Joseph Rayhawk Nilanjan Mukherjee Mentor Graphics Corporation

2 Reference A BISR Analyzer (CRESTA) for embedded DRAMs T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada H. Hidaka ITC 2000 BIST for Deep Submicron ASIC Memories with High Performance Application T.J. Powell, W.T. Cheng, J. Rayhawk, O. Samman, P. Policke, S. Lai ITC 2003

3 Outline What’s CRESTA ? What’s new ? Hardware Implement Conclusion

4 CRESTA Introduction Example Simulation Hardware Architecture Adv. & Disadv.

5 Introduction CRESTA = Comprehensive Real-time Exhaustive Search Test and Analysis At-Speed Multiple sub-analyzers try different order of spare rows/columns concurrently Detection Ability can become 100% Save address to repair by CAM

6 Algorithm During Memory BIST (for each Sub-analyzer n) ： If (Fail == 1) If ((Column_Addr not in CAM_C) && (Row_Addr not in CAM_R)) If (No more spare resouce) UnSuc[n] == 1 Else if (current spare resouce == row) CAM_R_cur = Row_Addr Point to next spare resouce Else if (current spare resouce == column) CAM_C_cur = Column_Addr Point to next spare resouce Post Memory BIST ： If (UnSuc != all ‘1’) Repairable, choose one of result that UnSuc[n] == 0 as your strategy Else Unrepairable

7 Example 5 x 5 Memory array 2 spare column 2 spare row 6 type BISR strategies  RRCC, RCRC, RCCR  CRRC, CRCR, CCRR

8 Sequence of Repair Analysis R-R-C-C2. R-C-R-C3. R-C-C-R 4. C-R-R-C5. C-R-C-R6. C-C-R-R RRRRRR RRRRRR CCCCCC CCCCCC

9 FSM of Sub-analyzer R1 Start C2 UnSuc C1 R2 [0] [2][3] [1] [4] [2][3] [1][2] [0] [4] [2] [0] Initialize [1] Fail [2] Pass [3] Fail & Match [4] Fail & Mismatch

10 Architecture CAM Array (Row) CAM Array (Column) L10 L11 L12 L13 Unsuc1 Fail Row Address Column Address UnSuc FSM WE 。。。

11 Adv & Disadv Advantage ：  At-Speed, shorter test cycle  Need not to store fail address  Area overhead only 1% Disadvantage ：  Dramatically increase area overhead with the number of spares  Only can deal with bit-oriented memory

12 Proposed Algorithm Algorithm for Linear Memory Example Simulation Modify for Multiplexed Memory

13 Linear Architecture Address width = 6 Word width = 4 Multiple Faults in a word cannot be achieved in one cycle Column Repair Vector (CRV) D0D1D2D3 0A0 1A1 2A2 63A63

14 Algorithm During Memory BIST ： If (Fail_Map != 0) If ((Fail_Map not in CRV) && (Row_Addr not in Spare_Rows)) If (No more spare resouce) unrepairable Else if (current spare resouce == row) Spare_Row = Row_Addr Point to next spare resouce Else if (current spare resouce == column) CRV = CRV | Fail_Map Point to next spare resouce Post Memory BIST ： If ((!unrepairable) && (# of 1 in CRV <= # of spare column)) Repairable Else Unrepairable Fail_Map = Fault Signature

15 Example of C-C-R-R C-C-R-R RCC CRV Fail_Map # of 1 in CRV == 5 > 2 Unrepairable !!

16 Example of C-R-R-C C-R-R-C RRCC CRV Fail_Map # of 1 in CRV == 2 <= 2 Repairable !!

17 Multiplexed Architecture Address width = 6 Word width = 2 MUX-level = 2 Row address = Address/MUX-level Column address = Address%MUX-level Designed for avoid intra-word coupling fault D0 D1 0A0A1A0A1 1A2A3A2A3 2A4A5A4A5 31A62A63A62A63

18 Modification for Multiplexed Architecture Method 1  Size of CRV = the # of bits in a row  Use the same algorithm in linear architecture  Area overhead is too large Method 2  Several word-size of CRVs as W-CRVs  Size of W-CRV = word size + length of MUX-level  # of W-CRVs = # of spare columns  Not only Compare with Column address but also MUX-level

19 Examples(1) MUX- level CRV

20 Examples(2) MUX- level CRV

21 Hardware

22 Architecture of BIST & BISRA BIST Controller Memory BISRA Controller Pass / Fail Repair Data Repairable Restart

23 R/W Operation with MBIST Full-Speed Setup Read 1 Setup Write 1 Setup Read 2 Setup Write 2 Setup Read 3 Read 1Write 1Read 2Write 2 Compare Read 1 Compare Read 2 Pass/Fail Read 1 Pass/Fail Read 2 Clock Cycle 1 Clock Cycle 1 Clock Cycle 1 Clock Cycle 1 Clock Cycle 1 Clock Addr / Ctrl Data Memory Compare Circuitry Output 。。。

24 MBIST Full-Speed Controller FSM Compare Capture Reference Data Con- trol Data Add- ress Compare Unit Memory Logic Pass / Fail

25 BISRA Controller with C(m+n, m) Engines Arbiter SRACAR SRACAR BISRA Engine Fail_Map Address Spare Resource Allocation Control and Report

26 BISRA Controller with 1 Engine SRACAR BISRA Engine Repair Strategy Reconfiguration (RSR) Fail_Map Address Restart

27 Reconfigure the Repair Strategy by LFSR By using LFSR “1” == Spare Row, “0” == Spare Column 1001→1010 → 0101 → 1100 → 0110 → 0011 Spare Resources Strategy Polynomial Initial Strategy 1R1C1+x R2C1+x R1C1+x R2C1+x+x 2 +x

28 Repair Strategy Selection Algorithm R R R RRR RR R C C C CC C C C C

29 Experiment Result TI TMS320C6414T with 90 nm tech. 3 controller, each with 7k to 8.5k gate 10% faster than normal functional frequency to detect performance related defect Controller #1Controller #2Controller #3 Memories22 single port31 single port32 single port RepairNoYes Mem Length80 – – Data Width32 – 646 – 4232 Clock Freq.400 MHz800 MHz

30 Conclusion Proposed a at-speed BISRA algorithms for word-oriented memories By modifying the CRESTA and by using CRV, multiple-failure in a word can handle at speed. Single or multiple repair engine for trade off. Repair strategies can either be generated by an on-chip LFSR or by an external ATE A branch and bound repair strategy selection algorithm to reduce repair time