Interconnect Efficient LDPC Code Design Aiman El-Maleh Basil Arkasosy Adnan Al-Andalusi King Fahd University of Petroleum & Minerals, Saudi Arabia Aiman El-Maleh Basil Arkasosy Adnan Al-Andalusi King Fahd University of Petroleum & Minerals, Saudi Arabia

2 OutlineOutline n Motivation n LDPC Code Overview n LDPC Codes and Cycles n Cycles Detection Algorithm n Area Constrained LDPC code Design n Experimental results n Conclusions n Motivation n LDPC Code Overview n LDPC Codes and Cycles n Cycles Detection Algorithm n Area Constrained LDPC code Design n Experimental results n Conclusions

3 MotivationMotivation n LDPC codes belong to a family of error correction systems with performance close to information- theoretic limits. n Selected for next-generation digital satellite broadcasting standard (DVB-S2), ultra high-speed Local Area Networks (10Gbps Ethernet LANs). n LDPC codes inherently more amenable to parallelization. n LDPC code design based on random code generation results in long interconnect wires, lower speed, higher power and less area utilization. n Objective to design interconnect-efficient LDPC codes with relatively good error correction performance. n LDPC codes belong to a family of error correction systems with performance close to information- theoretic limits. n Selected for next-generation digital satellite broadcasting standard (DVB-S2), ultra high-speed Local Area Networks (10Gbps Ethernet LANs). n LDPC codes inherently more amenable to parallelization. n LDPC code design based on random code generation results in long interconnect wires, lower speed, higher power and less area utilization. n Objective to design interconnect-efficient LDPC codes with relatively good error correction performance.

4 LDPC Codes Overview n LDPC codes linear block codes decoded by efficient iterative decoding. n An LDPC parity check matrix H represents the parity equations in a linear form codeword c satisfies the set of parity equations H c = 0. codeword c satisfies the set of parity equations H c = 0. each column in the matrix represents a codeword bit each column in the matrix represents a codeword bit each row represents a parity check equation each row represents a parity check equation n LDPC codes linear block codes decoded by efficient iterative decoding. n An LDPC parity check matrix H represents the parity equations in a linear form codeword c satisfies the set of parity equations H c = 0. codeword c satisfies the set of parity equations H c = 0. each column in the matrix represents a codeword bit each column in the matrix represents a codeword bit each row represents a parity check equation each row represents a parity check equation c 0  c 1  c 3 = 0 c 1  c 2  c 4 = 0 c 2  c 3  c 5 = 0 c 3  c 3  c 6 = 0

5 LDPC Codes Overview n LDPC codes can be classified as regular or irregular n H matrix is (W c,W r )-regular each row contains same number W r each row contains same number W r each column contains same number W c. each column contains same number W c. n LDPC codes represented by Tanner Graphs two types of vertices: Bit Vertices and Check Vertices two types of vertices: Bit Vertices and Check Vertices n Code Rate ratio of information bits to total number of bits in codeword n LDPC codes can be classified as regular or irregular n H matrix is (W c,W r )-regular each row contains same number W r each row contains same number W r each column contains same number W c. each column contains same number W c. n LDPC codes represented by Tanner Graphs two types of vertices: Bit Vertices and Check Vertices two types of vertices: Bit Vertices and Check Vertices n Code Rate ratio of information bits to total number of bits in codeword

6 LDPC Codes & Cycles n Existence of cycles (loops) in tanner graphs of LDPC codes impact performance. n A cycle of size K is a closed path of K edges visiting a vertex more than once, while visiting each edge in this path only once. n Possible cycles are of even sizes, starting by four. n Existence of cycles (loops) in tanner graphs of LDPC codes impact performance. n A cycle of size K is a closed path of K edges visiting a vertex more than once, while visiting each edge in this path only once. n Possible cycles are of even sizes, starting by four. 4-loop 6-loop

7 Cycle Detection Algorithm n Checking if an edge between the bit node i and the check node j creates a four loop: Find the set of all bit nodes K to which check node j is connected. Find the set of all bit nodes K to which check node j is connected. For each bit node k in K (k  i), find all the check nodes L that are connected to that node. For each bit node k in K (k  i), find all the check nodes L that are connected to that node. For each check node l in L (l  j), find all the bit nodes M that are connected to that node. For each check node l in L (l  j), find all the bit nodes M that are connected to that node. If node i is in M, then a four loop is detected If node i is in M, then a four loop is detected n Checking if an edge between the bit node i and the check node j creates a four loop: Find the set of all bit nodes K to which check node j is connected. Find the set of all bit nodes K to which check node j is connected. For each bit node k in K (k  i), find all the check nodes L that are connected to that node. For each bit node k in K (k  i), find all the check nodes L that are connected to that node. For each check node l in L (l  j), find all the bit nodes M that are connected to that node. For each check node l in L (l  j), find all the bit nodes M that are connected to that node. If node i is in M, then a four loop is detected If node i is in M, then a four loop is detected

8 Area Constrained LDPC Code Design n Randomly designed LDPC codes achieve good error correction performance. n Wire lengths in decoders can become very large. n Objective to design LDPC codes with constrains on interconnect wire length considerable decrease the signal delay considerable decrease the signal delay lowering interconnect routing congestion lowering interconnect routing congestion reducing chip area reducing chip area reducing power dissipation reducing power dissipation n Designed LDPC codes with 1024 bits and ½ rate. n Randomly designed LDPC codes achieve good error correction performance. n Wire lengths in decoders can become very large. n Objective to design LDPC codes with constrains on interconnect wire length considerable decrease the signal delay considerable decrease the signal delay lowering interconnect routing congestion lowering interconnect routing congestion reducing chip area reducing chip area reducing power dissipation reducing power dissipation n Designed LDPC codes with 1024 bits and ½ rate.

9 Area Constrained LDPC Code Design n Bit & check nodes laid out in a two-dimensional structure. n Connections btw. bit & check nodes constrained within a window of rows & columns. n Guarantees wire length bounded by a maximum length. n Example: Window(R,C) = (2,3). Window(R,C) = (2,3). Bit node 16 can only connect to check nodes (4,5,6,8,9,10). Bit node 16 can only connect to check nodes (4,5,6,8,9,10). n Bit & check nodes laid out in a two-dimensional structure. n Connections btw. bit & check nodes constrained within a window of rows & columns. n Guarantees wire length bounded by a maximum length. n Example: Window(R,C) = (2,3). Window(R,C) = (2,3). Bit node 16 can only connect to check nodes (4,5,6,8,9,10). Bit node 16 can only connect to check nodes (4,5,6,8,9,10).

10 Set of Check Nodes for a Bit Node Row#=  i/M  ; Col#= i mod M; Vertical Domain=R/2 Assigned check node =  (Col#+Row#*M)/2  ; t = 1; for each t  Vertical Domain { if (assigned check node + (t-1) * (M/2)) < No. check nodes Then assigned check node = assigned check node + ((t -1)* (M/2)) if (assigned check node + (t-1) * (M/2)) < No. check nodes Then assigned check node = assigned check node + ((t -1)* (M/2)) Add_Horizontal( assigned check node, Row# + (t-1) ) Add_Horizontal( assigned check node, Row# + (t-1) ) if (assigned check node – t * (M/2))  0 Then if (assigned check node – t * (M/2))  0 Then assigned check node = assigned check node – (t * (M/2)) assigned check node = assigned check node – (t * (M/2)) Add_Horizontal( assigned check node, Row# - t ) Add_Horizontal( assigned check node, Row# - t ) t = t + 1; t = t + 1;} NxM bit nodes, NxM/2 check nodes, window constraint (R, C)

11 Set of Check Nodes for a Bit Node Add_Horizontal (assigned check node, Row#) { Horizontal Domain =(C-1/)2; add the assigned check node; k = 1; for each k  Horizontal Domain { for each k  Horizontal Domain { if (assigned check node + k) < ((M/2) * (Row# +1)) Then if (assigned check node + k) < ((M/2) * (Row# +1)) Then add the check node “assigned check node + k” add the check node “assigned check node + k” if (assigned check node - k)  ((M/2) * Row#) Then if (assigned check node - k)  ((M/2) * Row#) Then add the check node “assigned check node - k” add the check node “assigned check node - k” k = k + 1; k = k + 1; }}

12 Experimental Results n Designed LDPC codes (3,6)-regular with 1024 bits and ½ rate. n LDPC codes randomly generated under given constraints. n Five LDPC codes for each criteria considered & best selected 4-loop free (4L), 4-loop free (4L), 6-loop free (6L), 6-loop free (6L), minimized 8-loop (M8L), minimized 8-loop (M8L), window constrained minimized 8-loop (WM8L). window constrained minimized 8-loop (WM8L). n LDPC codes with 32x32 layout of bit nodes and 32x16 layout of check nodes. n A constraint window (R, C)=(16, 15) is assumed. n Designed LDPC codes (3,6)-regular with 1024 bits and ½ rate. n LDPC codes randomly generated under given constraints. n Five LDPC codes for each criteria considered & best selected 4-loop free (4L), 4-loop free (4L), 6-loop free (6L), 6-loop free (6L), minimized 8-loop (M8L), minimized 8-loop (M8L), window constrained minimized 8-loop (WM8L). window constrained minimized 8-loop (WM8L). n LDPC codes with 32x32 layout of bit nodes and 32x16 layout of check nodes. n A constraint window (R, C)=(16, 15) is assumed.

13 Experimental Results n FER performance using simulations at different SNR points stopping criteria of 200 frame errors at SNR  2 and 200,000 code words for SNR>2. stopping criteria of 200 frame errors at SNR  2 and 200,000 code words for SNR>2. Iterative decoding performed for 64 iterations. Iterative decoding performed for 64 iterations. n Hardware comparisons based on VHDL model with parallel implem. of LDPC decoder from H matrix functions of check and variables nodes a dummy single gate functions of check and variables nodes a dummy single gate n Synthesis performed using Xilinx synthesis tools on Xilinx Spartan3 XC3S5000-fg900 FPGA optimized for area. n FER performance using simulations at different SNR points stopping criteria of 200 frame errors at SNR  2 and 200,000 code words for SNR>2. stopping criteria of 200 frame errors at SNR  2 and 200,000 code words for SNR>2. Iterative decoding performed for 64 iterations. Iterative decoding performed for 64 iterations. n Hardware comparisons based on VHDL model with parallel implem. of LDPC decoder from H matrix functions of check and variables nodes a dummy single gate functions of check and variables nodes a dummy single gate n Synthesis performed using Xilinx synthesis tools on Xilinx Spartan3 XC3S5000-fg900 FPGA optimized for area.

14 FER Comparison of LDPC codes SNR FER

15 Loop Count and Synthesis Results LDPC Code Structure No. of Loops Synthesis Slices used out of 33,280 Delay (ns) 468 4L , L , M8L002262, WM8L008702,

16 Post Place and Route Snapshots of Synthesized LDPC codes M8L WM8L

17 ConclusionsConclusions n Investigated design of interconnect-efficient LDPC codes that reduce area and delay of decoder while maintaining good error correction performance. n LDPC codes designed with loop constraints & window constraint on interconnect wire length. n Demonstrated possibility to deign LDPC codes that are interconnect efficient small performance impact compared to randomly unconstrained generated LDPC codes. small performance impact compared to randomly unconstrained generated LDPC codes. Less delay and routing congestion Less delay and routing congestion n Investigated design of interconnect-efficient LDPC codes that reduce area and delay of decoder while maintaining good error correction performance. n LDPC codes designed with loop constraints & window constraint on interconnect wire length. n Demonstrated possibility to deign LDPC codes that are interconnect efficient small performance impact compared to randomly unconstrained generated LDPC codes. small performance impact compared to randomly unconstrained generated LDPC codes. Less delay and routing congestion Less delay and routing congestion