Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Senior Design I Lecture 4 - Verilog 2 (Sequential Logic) Fall 2006 Read Verilog Handout Sections 1-6

ECE 491 Fall 2006Lecture 3 - Verilog Review 22 Today’s Outline  Verilog Review Part 2  Sequential Logic Basic Constructs Examples Registered vs. Combinational Outputs Lab 2 - Basic Sequential Logic Finite State Machines

ECE 491 Fall 2006Lecture 3 - Verilog Review 23 Sequential Design in Verilog - Basic Constructs  Describe edge-triggered behavior using:  always block with“edge event” clock-signal) clock-signal)  Nonblocking assignments ( <= clock-signal) begin output1 <= expression1;... output2 <= expression2;... end Registered Outputs for positive edge-trigger for negative edge-trigger Non-Blocking Assignments (deferred update)

ECE 491 Fall 2006Lecture 3 - Verilog Review 24 Simple Examples: Flip-Flop, Register module flipflop(d, clk, q); input d; input clk; output q; reg q; clk) q <= d; endmodule module flop3(clk, d, q); input clk; input[3:0] d; output [3:0] q; reg[3:0] q; clk) q <= d; endmodule D CLK QD Q 44

ECE 491 Fall 2006Lecture 3 - Verilog Review 25 Simple Example: Register with Reset  Synchronous - resets on clock edge if reset=1 module flopr(clk, reset, d, q); input clk; inputreset; input[3:0]d; output [3:0]q; reg[3:0] q; clk) if (reset) q <= 4’b0; else q <= d; endmodule D CLK Q 44 RESET

ECE 491 Fall 2006Lecture 3 - Verilog Review 26 Simple Example: Register with Reset  Asynchronous - resets immediately if reset=1 module flopr(clk, reset, d, q); input clk; inputreset; input[3:0]d; output [3:0]q; reg[3:0] q; clk or posedge reset) if (reset) q <= 4’b0; else q <= d; endmodule D CLK Q 44 RESET

ECE 491 Fall 2006Lecture 3 - Verilog Review 27 Another Example: Shift Register module shiftreg(clk, sin, q); input clk; inputsin; output [3:0]q; reg[3:0] q; clk) begin q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0]; q[0] <= sin; end endmodule Non-Blocking Assignments (update values after clock edge!)

ECE 491 Fall 2006Lecture 3 - Verilog Review 28 Shift Register Application module debounce (pb, clk_100Hz, pb_debounced); input pb; input clk_100Hz; output pb_debounced; reg pb_debounced; reg [3:0] shift_pb; (posedge clk_100Hz) begin shift_pb [3:0] <= {shift_pb [2:0], pb}; if (shift_pb == 4'b1111) pb_debounced <= 1; else pb_debounced <= 0; end endmodule // debounce What does this circuit do? How does it work?

ECE 491 Fall 2006Lecture 3 - Verilog Review 29 Another Example: 4-bit Counter  Basic Circuit: module counter(clk, Q); input clk; output [3:0] Q; reg [3:0] Q; // a signal that is assigned a value posedge clk ) begin Q <= Q + 1; end endmodule  Questions: How about carry?  Putting carry in this code would “register” carry  Result: carry delayed one clock cycle  Need to mix sequential & combinational logic carry <= (Q == 4’b1111); // WRONG!

ECE 491 Fall 2006Lecture 3 - Verilog Review 210 clock) or assign Combining Sequential and Combinational Outputs  General circuit - both registered and comb. outputs  Approach: multiple always blocks

ECE 491 Fall 2006Lecture 3 - Verilog Review 211 Registered Output Combinational Output Example: Adding carry to 4-bit Counter module counter(clk, Q, carry); input clk; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value assign carry = (Q == 4'b1111); posedge clk ) begin Q <= Q + 1; end endmodule

ECE 491 Fall 2006Lecture 3 - Verilog Review 212 Refining the Counter: Synchronous Clear module counter(clk, clr, Q, carry); input clk, clr; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value assign carry = (Q == 4'b1111); posedge clk ) begin if (clr) Q <= 4'd0; else Q <= Q + 1; end endmodule Q changes on clk edge (usually preferred)

ECE 491 Fall 2006Lecture 3 - Verilog Review 213 Refining the Counter: Asynchronous Clear module counter(clk, clr, Q, carry); input clk, clr; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value assign carry = (Q == 4'b1111); posedge clr or posedge clk ) begin if (clr) Q <= 4'd0; else Q <= Q + 1; end endmodule Q changes on clk edge OR on reset

ECE 491 Fall 2006Lecture 3 - Verilog Review 214 Lab 2 Goals  Gain experience using Verilog for sequential logic  Gain experience using parameterized modules  Gain experience interfacing FPGA to I/O  Design building blocks that will be useful later  Design & debug a complete sequential circuit (stopwatch)

ECE 491 Fall 2006Lecture 3 - Verilog Review 215 Lab 2 Overview 1.Parameterized counter (base on BCD example)  BW parameter: bitwidth  M parameter: counter modulus (counts from 0..M-1)  Inputs: clk, reset, enb  Outputs: Q, carry

ECE 491 Fall 2006Lecture 3 - Verilog Review 216 Lab 2 Overview (cont’d) 2.Write to divide 50 MHz clock down to 100 Hz  Use parameterized counter to divide by 250,000  Use “T flip-flop” to give 50% duty cycle

ECE 491 Fall 2006Lecture 3 - Verilog Review 217 Lab 2 Overview (cont’d) 3.Review debouncer discussed in class last time 4. Design a stopwatch accurate to 1/100 sec.  Buttons: clear - resets time to sec stop/start - alternately stops/starts count

ECE 491 Fall 2006Lecture 3 - Verilog Review 218 Lab 2 Overview (cont’d) 4.Design a Stopwatch (cont’d)  Design ideas Use BCD counters for stopwatch digits Use debouncer for “run/start”, “clear buttons” Use a simple FSM to respond to run/start button press Build a sequential circuit or counter that time-multiplexes digits to the segment_out port

ECE 491 Fall 2006Lecture 3 - Verilog Review 219 Review: BCD Counter  How can it be parameterized? module bcdcounter(clk, reset, enb, Q, carry); input clk, reset, enb; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value assign carry = (Q == 9) & enb; posedge clk ) begin if (reset) Q <= 0; else if (enb) begin if (carry) Q <= 0; else Q <= Q + 1; end endmodule

ECE 491 Fall 2006Lecture 3 - Verilog Review 220 State Machine Design  Traditional Approach:  Create State Diagram  Create State Transition Table  Assign State Codes  Write Excitation Equations & Minimize  HDL-Based State Machine Design  Create State Diagram (optional)  Write HDL description of state machine  Synthesize

ECE 491 Fall 2006Lecture 3 - Verilog Review 221 Review - State Transition Diagrams  "Bubbles" - states  Arrows - transition edges labeled with condition expressions  Example: Car Alarm arm door honk clk f clk = 1Hz

ECE 491 Fall 2006Lecture 3 - Verilog Review 222 Review - State Transition Table  Transition List - lists edges in STD PSConditionNSOutput IDLEARM' + DOOR'IDLE0 IDLEARM*DOORBEEP0 BEEPARMWAIT1 BEEPARM'IDLE1 WAITARMBEEP0 WAITARM'IDLE0

ECE 491 Fall 2006Lecture 3 - Verilog Review 223 Coding FSMs in Verilog - “Explicit” Style  Clocked always block - state register  Combinational always block -  next state logic  output logic

ECE 491 Fall 2006Lecture 3 - Verilog Review 224 Coding FSMs in Verilog - Code Skeleton  Part 1 - Declarations module fsm(inputs, outputs); input...; reg...; parameter [NBITS-1:0] S0 = 2'b00; S1 = 2'b01; S2 = 2b'10; S3 = 2b'11; reg [NBITS-1 :0] CURRENT_STATE; reg [NBITS-1 :0] NEXT_STATE; State Codes State Variable

ECE 491 Fall 2006Lecture 3 - Verilog Review 225 Coding FSMs in Verilog - Code Skeleton  Part 2 - State Register, Logic Specification clk) begin CURRENT_STATE <= NEXT_STATE; end or xin) begin case (CURRENT_STATE) S0:... determine NEXT_STATE, outputs S1 :... determine NEXT_STATE, outputs end case end // always endmodule

ECE 491 Fall 2006Lecture 3 - Verilog Review 226 FSM Example - Car Alarm  Part 1 - Declarations, State Register module car_alarm (arm, door, reset, clk, honk ); input arm, door, reset, clk; output honk; reg honk; parameter IDLE=0,BEEP=1,HWAIT=2; reg [1:0] current_state, next_state; reset or posedge clk) if (reset) current_state <= IDLE; else current_state <= next_state;

ECE 491 Fall 2006Lecture 3 - Verilog Review 227 FSM Example - Car Alarm  Part 2 - Logic Specification or arm or door) case (current_state) IDLE : begin honk = 0; if (arm && door) next_state = BEEP; else next_state = IDLE; end BEEP: begin honk = 1; if (arm) next_state = HWAIT; else next_state = IDLE; end

ECE 491 Fall 2006Lecture 3 - Verilog Review 228 FSM Example - Car Alarm  Part 3 - Logic Specification (cont’d) HWAIT : begin honk = 0; if (arm) next_state = BEEP; else next_state = IDLE; end default : begin honk = 0; next_state = IDLE; end endcase endmodule

ECE 491 Fall 2006Lecture 3 - Verilog Review 229 FSM Example - Verilog Handout  Divide-by-Three Counter S0 out=0 S1 out=0 S1 out=1 reset

ECE 491 Fall 2006Lecture 3 - Verilog Review 230 Verilog Code - Divide by Three Counter Part 1 module divideby3FSM(clk, reset, out); inputclk; inputreset; outputout; reg[1:0] state; reg[1:0]nextstate; parameterS0 = 2’b00; parameterS1 = 2’b01; parameterS2 = 2’b10; // State Register clk or posedge reset) if (reset) state <= S0; else state <= nextstate;

ECE 491 Fall 2006Lecture 3 - Verilog Review 231 Verilog Code - Divide by Three Counter Part 2 // Next State Logic case (state) S0: nextstate = S1; S1: nextstate = S2; S2: nextstate = S0; default: nextstate = S0; endcase // Output Logic assign out = (state == S2); endmodule

ECE 491 Fall 2006Lecture 3 - Verilog Review 232 Example from VLSI: “01 Recognizer”  Output 1 when input=0 for 1 clock cycle, then 1 bit1bit2 input=0 / output=0 0 / 0 1 / 1 1 / 0 input output clk

ECE 491 Fall 2006Lecture 3 - Verilog Review 233 Verilog Code - 01 Recognizer Part 1 module recognizer (clk, reset, rin, rout); input clk, reset, rin; output rout; reg rout; parameter [1:0] bit1=2'b00, bit2=2'b01; reg [1:0] current_state, next_state; clk) if (reset) current_state = bit1; else current_state <= next_state; or rin) case (current_state) bit1: begin rout = 1'b0; if (rin == 0) next_state = bit2; else next_state = bit1; end

ECE 491 Fall 2006Lecture 3 - Verilog Review 234 Verilog Code - 01 Recognizer Part 1 bit2: begin if (rin == 1'b0) begin rout = 1'b0; next_state = bit2; end else begin rout = 1'b1; next_state = bit1; end default: begin rout = 1'b0; next_state = bit1; end endcase endmodule

ECE 491 Fall 2006Lecture 3 - Verilog Review 235 Coming Up  More about event-driven simulation  Verification and Testbenches