Sequential PLD timing Registers Counters Shift registers EE365 Sequential PLD timing Registers Counters Shift registers

Sequential PLD timing parameters

Timing contd.

Multibit registers and latches 74x175

8-bit (octal) register 74x374 3-state output

Other octal registers 74x377 74x273 asynchronous clear Non-three state output 74x377 clock enable no tristate-buffer

Octal latch 74x373 Register vs. latch, what’s the difference? Output enable Latch-enable input “C” or “G” Register vs. latch, what’s the difference? Register: edge-triggered behavior Latch: output follows input when G is asserted

Counters Any sequential circuit whose state diagram is a single cycle. RESET

LSB Synchronous counter Serial enable logic MSB

LSB Synchronous counter Parallel enable logic MSB

74x163 MSI 4-bit counter

74x163 internal logic diagram XOR gates embody the “T” function Mux-like structure for loading

Counter operation Free-running 16 Count if ENP and ENT both asserted. Load if LD is asserted (overrides counting). Clear if CLR is asserted (overrides loading and counting). All operations take place on rising CLK edge. RCO is asserted if ENT is asserted and Count = 15.

Free-running 4-bit ’163 counter “divide-by-16” counter

Modified counting sequence Load 0101 (5) after Count = 15 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5, 6, … “divide-by-11” counter

Another way Clear after Count = 1010 (10) trick to save gate inputs Clear after Count = 1010 (10) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2, 3, … “modulo-11” or “divide-by-11” counter

Counting from 3 to 12

Cascading counters RCO (ripple carry out) is asserted in state 15, if ENT is asserted.

Decoding binary-counter states

Decoder waveforms Glitches may or may not be a concern.

Glitch-free outputs Registered outputs delayed by one clock tick. We’ll show another way to get the same outputs later, using a shift register.

Shift registers For handling serial data, such as RS-232 and modem transmission and reception, Ethernet links, etc. Serial-in, serial-out

Serial-to-parallel conversion Use a serial-in, parallel-out shift register

Parallel-to-serial conversion Use parallel-in, serial-out shift register mux

Do both Parallel-in, parallel-out shift register

“Universal” shift register 74x194 Shift left Shift right Load Hold

One stage of ’194

Shift-register counters Ring counter

Johnson counter “Twisted ring” counter

LFSR counters Pseudo-random number generator 2n - 1 states before repeating Same circuits used in CRC error checking in Ethernet networks, etc.