Introduction to Make Updated by Prasad Spring 2000

What is Make ? Utility for maintaining up-to-date versions of programs. Based on rules defined in a Makefile, it will rebuild executables by determining which program modules need to be recompiled when changes are made to the original source code. Particularly useful for big software projects with large number of source files that depend on one another in complex ways. Automates the process of compiling and linking your programs during the development phase.

Hierarchy dependency for a Project Output Executable Main.o Funct1.oFunct2.o def.hMain.cdef.hFunc1.c Func2.c def.h

Sample Make file for the Project Output: Main.o Funct1.o Funct2.o cc –o Output Main.o Funct1.o Funct2.o Main.o: Main.c def.h cc –c Main.c Funct1.o: Funct1.c def.h cc –c Funct1.c Funct2.o: Funct2.c def.h cc –c Func2.c

What a rule looks like Rules are of the following form: target ….. : dependencies ….. command ……….. target: Name of a file generated by the program (executables or Object files) dependencies: List of files that are used as input to create the target. command: A command is an action that make carries out to produce the target. Can have more than one command.

Make features … Using Variables in Make –Can declare and define values for variables and can reuse them in the rules. –Example: objects = program.o foo.o utils.o program : $(objects) cc -o program $(objects) $(objects) : defs.h

Make Features … Can use built in functions for Text processing. (however cannot define new functions within Makefile) Syntax: ${function arguments} Examples: $(subst from,to,text) shell function can be used to communicate with world outside of make. Example: files := $(shell echo *.c)

Make Features …. Can use conditionals in Make files libs_for_gcc = -lgnu normal_libs = foo: $(objects) ifeq ($(CC),gcc) $(CC) -o foo $(objects) $(libs_for_gcc) else $(CC) -o foo $(objects) $(normal_libs) endif