Lab 10 RT methodology (cont’d) Example 1 – a counter Example 2 – a repetitive-adder multiplier.

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Presentation transcript:

Lab 10 RT methodology (cont’d) Example 1 – a counter Example 2 – a repetitive-adder multiplier

RT Methodology - Review Key characteristics: Use registers to store intermediate data. Use a data path to realize all the required operations. Use a control path to specify the order of the register operations.

Extended example 1: a counter

Example: a counter Specification: When start = 1 and reset = 0, the system starts counting at each rising edge. If inc = 0, counter is incremented by one; otherwise, it is incremented by two. A synchronous reset is implemented to reset the counter to zero. counter represents the current value of the counter. When counter reaches a value of six or greater, the output end is set to one for a clock period and the counter stops. Finally, the counter is set to zero and the system waits for start = 1 again. Counter Register to be used

A data-path for the counter

A control path for the counter

Top File

VHDL Code Register

VHDL Code Adder

VHDL Code Multiplexer

Data path

Control path

Top

Extended example a: a repetitive-adder multiplier

Repetitive Addition Multiplier Repetitive-Addition Multiplier is a sequential method to multiple. It uses just one adder unit and a subtracter unit to multiply. Sequential methodology is used when area is critical compared timing. Example: 7x5= =35; i.e., add 7 five times.

Algorithm

ASM Input: –a_in, b_in: 8-bit unsigned –clk, reset –start: command Output: –r: 16-bit unsigned –ready: status

Data Path Construction of the data path 1- List all RT operations 2- Group RT operation according to the destination register 3- Add combinational circuit/mux 3- Add status circuits

Control Path Construction of the data path 1- Next state process 2- Output process - Moore 3- Output process - Mealy 3- Update state process