1 Integration of the HV Distribution System to the First TRD Super Module P. Mantzaridis, A. Markouizos, P. Mitseas, A. Petridis, S. Potirakis, M. Tsilis,

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Presentation transcript:

1 Integration of the HV Distribution System to the First TRD Super Module P. Mantzaridis, A. Markouizos, P. Mitseas, A. Petridis, S. Potirakis, M. Tsilis, M. Vassiliou Athens University Workshop on the DCS for the TRD Heidelberg, January 2007

2 Outline Installation of the first HVDS at CERN Specifications of the HVDS Control of the HVDS Performance of the HVDS Current Status (hardware, software)

3 Installation of the first HVDS at CERN (October 2006)

4 Installed Hardware at CERN 1+1 Crates ( positions: 007_9, 007_16 ) 1+1 DCS Boards ( with auxiliary DCS cards ) 1+1 Backplanes supplies the Master HV to each card distributes the isolated LV to the active components enables the CAN bus communication 5 Anode + 5 Drift Cards 3+3 isolated LV Auxiliary Power Supply Cards LV Power Supplies (5V, ±12V)

5 Specifications of the HVDS Anode Voltage - dynamical range900 – 1900 V - ramp-up rate30 V/s - ramp-down rate100 V/s - voltage stability  V < 50 mV - voltage readout10 Hz - max. current 7  A - response time < 50 ms (e.g. overcurrent)

6 Specs. (cont) Drift Voltage - dynamical range1450 – 2500 V - ramp-up rate30 V/s - ramp-down rate100 V/s - voltage stability  V < 50 mV - voltage readout 10 Hz - max. current230  A - response time < 50 ms (e.g. overcurrent)

7 Control of the HVDS

8 The TRD Overview Drawing

9 DCS Board 0 Crate 0 DCS Board 1 (Optional) Module 2 (Internal architecture similar to module 0) Crate 1 (Internal architecture similar to crate 0) Module 0 Card 0 Card 1 Card 2 Card 3 Card 4 Module 1 (Internal architecture similar to module 0) Architecture of the CAN network

10 HVDS Card Control Panel

11 ISEG Control Panel (G. Tsiledakis)

HVDS Channel Control Panel (Test on the SM 1 at CERN, 8/10/2006)

13 Ramping and Status Procedures

14 Error Messages Voltage Errors  Over Voltage  message: max allowed voltage is exceeded  action: voltage is set to the max allowed value  Under Voltage  message: min allowed voltage is out of range  action: voltage is set to the max allowed value  Limits Error  message: set value is out of limits  action: limit is set to the default value Current Errors (Hardware Error)  Over Current  alarm: max allowed current is exceeded or a short-circuit occurred Ramping Errors  Ramping Rate  message: max allowed rate is exceeded  action: rate is set to the max allowed value  Ramping End Value  message: end value is out of limits  Action: value is set to the max allowed  Limits Error  message: set value is out of limits  action: limit is set to the default value

15 HV State Diagram (G. De Cataldo)

16 Control of the HVDS Performance of the HVDS

17 Voltage Stability Test on the Detector at HD ( ) Voltage Measurements

18 Current Stability Test on the Detector at HD ( ) Operating 3 channels from one HV Anode Card Current Measurements

19 Voltage Stability Measurements on the SM1 at CERN (9/10/2006) 6 anode channels HV set at 1450 V

20 Voltage Resolution Measurement on the SM1 at CERN (9/10/2006) Anode ChannelHV set at 1450 V

21 Long Term Voltage Stability Test (Athens - Jan 2007) ΔV (FWHM) < 30 mV ΔV / V < 1.6 E-5

22 Control of the HVDS Current Status

23 Hardware New Schroff Crate + LV Power Supply Two parallel orders to Q-Print 2 Anode + 2 Drift cards for testing purposes 30 (+10) Anode + 30 (+10) Drift cards to power 6 Supermodules + 5 Backplanes, Auxiliary DCS cards, connector card, Isolated PS cards Define testing procedure Magnetic field tests of a full crate at CERN Installation of the 2+2 HV Crates at P2 Documentation

24 Archiving Amanda Server Manager (AliRoot) ORACLE Database Alarm Handling Recipes and logical views Integration to the TRD-DCS PVSS project according to the ALICE DCS guidelines Implementation of the FSM Installation of final software project at CERN Documentation Software

25 Thank you!