Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures1 Machine instructions execution steps (1) FETCH = Read the instruction from memory using PC as the ptr (2) DECODE = Decode the instruction (decide what to do next) and read the necessary registers (1 or 2) (3) EXECUTE = Calculate the result or a memory address by the ALU (4) MEMORY = Use the ALU result to access the memory if required (read data in load, write data in store) (5) WRITE BACK = If required, write the result into the appropriate register

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures2 We “read” during the entire CK cycle We write at the end of the CK cycle cycle time rising edge falling edge The control lines: Those are produced by the CK. Every rising edge of the CK causes the appropriate changes of the control lines.

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures3 A simplified MIPS CPU The connections shown above supports all phases of R-type and I-type instructions. Our design will support add, sub, or, xor, and, slt, lw, sw, beq, j instructions. We should be able to add more instructions, e.g., bne, addi, jal, jr.

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures4 The basic CPU parts needed for the Fetch phase: Instruction Address Instruction Memory Add Sum It is clear that we need a PC register, a memory to store the instructions and an adder to increment the PC.

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures5 The Fetch phase Add 4 PC Read address Instruction memory 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures6 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Instruction Memory PC Adde r 4 ck 6 [31:26] 6 [5:0]= funct PC0x x Memory outputNew Memory output fetch 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures7 The general register file (GPR). This unit is required for the decode phase (and for the Write Back phase) Read register 1 Registers Read register 2 Write register Write Data Read data1 Read data2 The registers indices Data

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures8 Arithmetic Logic operation Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 ALU Zero ALU operation ALU result Instruction ALU result ALU operation The basic operation we demonstrate is an R-type instruction

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures9 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct PC0x x Rs, RtALU inputsnew ALU inputs Memory outputNew Memory output fetch decode fetch decode 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures10 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures11 The internal structure of the Register File 32 Read data 2 write data Read data Rd reg 2 (= Rt) Rd reg 1 (= Rs) RegWrite Wr reg (= Rd) 32 E We read 2 different registers from the 2 outputs simultaneously We write to one of the registers (in the next rising edge of the CK).

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures12 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures13 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU ck 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures14 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PC ALU ck 4 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures15 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 6 [5:0]=funct ALU control 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures16 Building the Load and Store operations Read address Data memory Write address Write data Read data Write Read Here we need Data memory from which we read (and to which we write). We also need to perform sign extension to the 16 bit imm. 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures17 A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D. Out 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures18 A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D. Out 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures19 A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D. Out 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures20 A CPU capable of lw & sw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=0 16 [15:0] 5 add Sext 16->32 Data Memory D.In Address MeWrite=1 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures21 A CPU capable of R-type & lw instructions (principle) 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control 5 [15:11]=Rd Address 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures22 A CPU capable of R-type & lw instructions 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control Rd Address D. Out 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures23 A CPU capable of R-type & lw/sw instructions 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control Rd Address D.In D. Out MemWrite 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures24 Elements needed for Branch instruction ALU Zero Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 Instruction Adder Sum Shift left2 Sigh Extend Branch Target The zero signal is transferred to the control unit as the result of the comparison 1632 PC+4 after Fetch In addresses, we always shift left by two bits 32

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures25 Combining all of the instructions Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 Zero ALU result Data Sign extend 32 Read address memory Write address Write data Read data Write Read 16 Add 4 PC M u x Read address Instruction memory ADD ALU result Shift left2 M u x M u x

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures26 Where is the CPU? CPU Instruction Memory Data Memory PC

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures27 Control lines PC Instruction memory Read address Instruction Add M u x Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 4 M u x ALU operation 3 RegWrite MemRead MemWrite PCSrc ALUSrc MemtoReg ALU result Zero ALU Data memory Address Write data Read data M u x Sign extend Add ALU result Shift left 2

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures28 Control PC Instruction memory Read address Instruction [31–0] Instruction [20–16] Instruction [25–21] Add Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch R register 2 Sign extend Shift left 2 M u x 1 ALU result Zero Data memory Write data Rea d dat a M u x 1 Instruction [15–11] ALU control ALU Address

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures29 Control

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures30 ALU control ALU control input 000 AND 001OR 010add 110subtract 111set-on-less-than (sign of rs-rt -> rd) 00 = lw, sw (add) 01 = beq (sub) 10 = arithmetic (see table) ALUop: Operation[2:0]

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures The Jump instruction 4 bits 26 bits 2 bits Jump address in words: Jump address in bytes: … … Final jump address in bytes: Adding the 4 MSBs: The instruction: J 101 … means that the next instruction is in address 101 … (actually in word 101 … )

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures32 Jump Shift left 2 PC Instruction memory Read address Instruction [31–0] Data memory Read data Write data Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] Instruction [20–16] Instruction [25–21] Add ALU result Zero Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch Jump RegDst ALUSrc I sult M u x 0 10 ALU Shift left Address

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures33 End of single cycle implementation