Paul Rubinov TriP-t & AFEII status. AFE and CFT 9 o K VLPC (x512) AFE DISCRADC Discriminator output every 396 nsec for L1 Amplitude signal readout for.

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The group is developing readout electronics for initial use with the prototype test-stand at Fermilab. This work will contribute towards the design and.

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Presentation transcript:

Paul Rubinov TriP-t & AFEII status

AFE and CFT 9 o K VLPC (x512) AFE DISCRADC Discriminator output every 396 nsec for L1 Amplitude signal readout for L3 and offline 8 photons 80 fC Central Fiber Tracker cylinder

Overview Ancient history STOP build/test TriP for 132ns running TriP works very well at 396ns and adding time info can help CFT a lot. Build TriP-T Build AFEII prototype Summer 04 milestone Aug 04 Build AFEII (with time Info) by end of 2005 AFE1 problems

AFEII proto current status Schematic design is 99% complete. …an internal review has been completed. The review committee made a number of suggestions (minor) and these are being implemented. Layout of the board is about 80% complete… However, this is going very slowly. Still 3 weeks work left. This puts the work about 3-6 weeks behind schedule. Has impact on D0. Test of AFE II prototypes with beam this August is now NOT likely. Specifications for the new microcontroller code requirements are 75% complete… Design of the FPGA is 75% complete…

TriP  The existing TriP ASIC (7000 die on hand)  Lots of testing over about 18 months- described in Fermi TM 2226, 2227 and 2228

TriP-t: the new idea  About 1% additional components:  7bits t-info offline: 120ns full scale=> 2ns time => ~35cm resolution in Z

TriP-t current status  The chip designers are chip designing.  End date is given as Aug ’04  The new chip is the “critical path” item for the project u Assuming D0 makes decision to use Tript  Some prep work going on now u We will need new packaging u We had some concerns about features used on the new chip, but where not used on the old (current!) TriP chip.

TriP-t prep work  Bench testing  New package