Parking Pal Presentation #6 Team M1: Anna Kochalko Chris Moody Hong Tuck Liew John Wu Project Manager: Kartik Murthy October 10, 2007 Schematic Review! Your digital parking meter of the future!

Status Project Chosen Options explored and eliminated Wrote Java Implementation Specification defined Verilog obtained/modified Test Benches Schematic Design  Layout*  Simulations

Encryption Block Parts in Encryption Block:  2x 16 bits register  16 bits Mux  32 bits Mux  FSM(encryption)  Encryptor (Small Encryption Block)

FSM Encryption

FSM Encryption (Wave)

Encryption Cell

Encryption Cell (Wave)

Full Encryption Block

Full Encryption Wave

Tickets Block This block is responsible for determining how much time a car has left to park, and whether or not a car should be ticketed. Major Components: –11-Bit Adder, 11-Bit Subtractor, 11-Bit Comparator.

SRAM  Included in the following slides are simulation results for an SRAM cell and mult-adder block.  Design decision made:  Not pre-charging for reading because it makes it faster not more power efficient

SRAM Cell

SRAM Cell Wave

SRAM FSM

SRAM FSM WAVE

Overall SRAM

Full SRAM Wave

7-Segment Display  Included in the following slides are simulation results for a 7-Segment Display block

Binary to BCD (4 bits)

Parallel to Serial

7-Seg Display Cell

Full 7-Seg Display Block

Full 7-Seg Display(Wave)

Overall Design Schematic

Layout*

Things to Do Power FSM Layout More Layout