331 W10.1Spring :332:331 Computer Architecture and Assembly Language Spring 2005 Week 10 Building a Multi-Cycle Datapath [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

331 W10.2Spring 2005 Head’s Up  This week’s material l Multicycle MIPS datapath implementation -Reading assignment – PH 5.5 and C.3

331 W10.3Spring 2005 Review: Single Cycle Data and Control Path Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Instr[31-26] Branch Shift left Jump 28 Instr[25-0] 26 PC+4[31-28] 32

331 W10.4Spring 2005 Disadvantages of the Single Cycle Datapath  Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction l especially problematic for more complex instructions like floating point multiply  Is wasteful of area since some functional units must be duplicated since they can not be “shared” during an instruction execution l e.g., need separate adders to do PC update and branch target address calculations, as well as an ALU to do R- type arithmetic/logic operations and data memory address calculations

331 W10.5Spring 2005 Multicycle Implementation Overview  Each step in the execution takes 1 clock cycle  An instruction takes more than 1 clock cycle to complete  Not every instruction takes the same number of clock cycles to complete  Multicycle implementations allow l functional units to be used more than once per instruction as long as they are used on different clock cycles, as a result -only need one memory -need only one ALU/adder l faster clock rates l different instructions to take a different number of clock cycles

331 W10.6Spring 2005 The Multicycle Datapath – A High Level View Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout  Registers have to be added after every major functional unit to hold the output value until it is used in a subsequent clock cycle

331 W10.7Spring 2005 Clocking the Multicycle Datapath Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout System Clock MemWriteRegWrite clock cycle

331 W10.8Spring 2005  Break up the instructions into steps where each step takes a cycle while trying to l balance the amount of work to be done in each step l restrict each cycle to use only one major functional unit  At the end of a cycle l Store values needed in a later cycle by the current instruction in a state element (internal register) not visible to the programmer IR – Instruction Register MDR – Memory Data Register A and B – register file read data registers ALUout – ALU output register l All (except IR) hold data only between a pair of adjacent clock cycles (so don’t need a write control signal) l Data used by subsequent instructions are stored in programmer visible state elements (i.e., register file, PC, or memory) Multicycle Approach

331 W10.9Spring 2005 The Complete Multicycle Data with Control Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

331 W10.10Spring 2005  Reading/writing to l any of the internal registers or the PC occurs (quickly) at the end of a clock cycle l reading/writing to the register file takes ~50% of a clock cycle since it has additional control and access overhead (reading can be done in parallel with decode)  Have to add multiplexors in front of several of the functional unit inputs because the functional units are shared by different instruction cycles  All operations occurring in one step occur in parallel within the same clock cycle l This limits us to one ALU operation, one memory access, and one register file access per step (per clock cycle) Multicycle Approach, con’t

331 W10.11Spring 2005  Instruction Fetch  Instruction Decode and Register Fetch  R-type Instruction Execution, Memory Read/Write Address Computation, Branch Completion, or Jump Completion  Memory Read Access, Memory Write Completion or R-type Instruction Completion  Memory Read Completion (Write Back) INSTRUCTIONS TAKE FROM CYCLES! Five Instruction Steps

331 W10.12Spring 2005  Use PC to get instruction from the memory and put it in the Instruction Register  Increment the PC by 4 and put the result back in the PC  Can be described succinctly using RTL "Register- Transfer Language“ IR = Memory[PC]; PC = PC + 4; Can we figure out the values of the control signals? What is the advantage of updating the PC now? Step 1: Instruction Fetch

331 W10.13Spring 2005 Fetch Control Signals Settings Start Instr Fetch

331 W10.14Spring 2005  Don’t know what the instruction is yet, so can only l Read registers rs and rt in case we need them l Compute the branch address in case the instruction is a branch  RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2);  Note we aren't setting any control lines based on the instruction (since we are busy "decoding" it in our control logic) Step 2: Instruction Decode and Register Fetch

331 W10.15Spring 2005 Datapath Activity During Instruction Decode Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

331 W10.16Spring 2005 Decode Control Signals Settings Start Instr Fetch Decode Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

331 W10.17Spring 2005  ALU is performing one of four functions, based on instruction type  Memory reference (lw and sw): ALUOut = A + sign-extend(IR[15-0]);  R-type: ALUOut = A op B;  Branch: if (A==B) PC = ALUOut;  Jump: PC = PC[31-28] || (IR[25-0] << 2); Step 3 (instruction dependent)

331 W10.18Spring 2005 Datapath Activity During Instruction Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

331 W10.19Spring 2005 Execute Control Signals Settings Start Instr Fetch Decode Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

331 W10.20Spring 2005  Memory reference: MDR = Memory[ALUOut]; -- lw or Memory[ALUOut] = B; -- sw  R-type instruction completion Reg[IR[15-11]] = ALUOut;  Remember, the register write actually takes place at the end of the cycle on the clock edge Step 4 (instruction dependent)

331 W10.21Spring 2005 Datapath Activity During Memory Access Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

331 W10.22Spring 2005 Memory Access Control Signals Settings Start Instr Fetch Decode Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite

331 W10.23Spring 2005  All we have left is the write back into the register file the data just read from memory for lw instruction Reg[IR[20-16]]= MDR; What about all the other instructions? Step 5: Memory Read Completion (Write Back)

331 W10.24Spring 2005 Datapath Activity During Write Back Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

331 W10.25Spring 2005 Write Back Control Signals Settings Start Instr Fetch Decode Write Back Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 MemRead IorD=1 PCWriteCond=0

331 W10.26Spring 2005 RTL Summary StepR-typeMem RefBranchJump Instr fetch IR = Memory[PC]; PC = PC + 4; Decode A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2); Execut e ALUOut = A op B; ALUOut = A + sign-extend (IR[15-0]); if (A==B) PC = ALUOut; PC = PC[31-28] ||(IR[25-0] << 2); Memor y access Reg[IR[15- 11]] = ALUOut; MDR = Memory[ALUOut]; or Memory[ALUOut] = B; Write- back Reg[IR[20-16]] = MDR;

331 W10.27Spring 2005  How many cycles will it take to execute this code? lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label #assume not add $t5, $t2, $t3 sw $t5, 8($t3) Label:...  What is going on during the 8 th cycle of execution?  In what cycle does the actual addition of $t2 and $t3 takes place?  In what cycle is the branch target address calculated? Simple Questions

331 W10.28Spring 2005  Multicycle datapath control signals are not determined solely by the bits in the instruction l e.g., op code bits tell what operation the ALU should be doing, but not what instruction cycle is to be done next  We’ll use a finite state machine for control l a set of states (current state stored in State Register) l next state function (determined by current state and the input) l output function (determined by current state and the input)  We’ll use a Moore machine (so control signals based only on current state) Multicycle Control Combinational control logic State Reg Inst Opcode Datapath control points Next State...

331 W10.29Spring 2005 Finite State Machine Implementation Combinational control logic State Reg Inst[31-26] Next State Inputs Outputs Op0Op1Op2Op3Op4Op5 PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource ALUOp ALUSourceB ALUSourceA RegWrite RegDst System Clock

331 W10.30Spring 2005 Datapath Control Outputs Truth Table OutputsInput Values (Current State[3-0]) PCWrite PCWriteCon d X X IorD0XX1X1XXXX MemRead1XX1XXXXXX MemWrite IRWrite MemtoRegXXXX1XX0XX PCSource00XX 0110 ALUOp00 XX 10XX01XX ALUSrcB011110XX 00XX00XX ALUSrcA001XXX1X1X RegWrite RegDstXXXX0XX1XX

331 W10.31Spring 2005 Next State Truth Table Current State [3- 0] Inst[31-26] (Op[5-0]) (R-type) (jmp) (beq) (lw) (sw) Any other illegal 0010XXXX illegal 0011XXXX 0100XXXXillegal 0100XXXX 0000XXXXillegal 0101XXXX 0000illegal XXXX illegal XXXX illegal 1000XXXX 0000XXXX illegal 1001XXXX0000XXXX illegal