ENEE 408C Lab Capstone Project: Digital System Design Fall 2005 Sequential Circuit Design

Finite State Machines A finite state machine (FSM) is a circuit designed to sequence through specific patterns of states in a sequential manner. A finite state machine (FSM) is a circuit designed to sequence through specific patterns of states in a sequential manner. Each state is represented by a binary value. Each state is represented by a binary value. An FSM contains a sequential state register, and combinational next-state and output logic. An FSM contains a sequential state register, and combinational next-state and output logic.

Mealy and Moore Machines A Mealy state machine has outputs that are a function of the current state AND the primary inputs. A Mealy state machine has outputs that are a function of the current state AND the primary inputs. A Moore state machine has outputs that are a function of the current state only. A Moore state machine has outputs that are a function of the current state only. A combined Mealy/Moore state machine has both. A combined Mealy/Moore state machine has both. Numerous FSM ‘dialects’ exist in design tools. Numerous FSM ‘dialects’ exist in design tools.

State Table InputAInputHold Current State Next State OutputY_MeOutputY_Mo 0X X X X XX X XX

State Encoding Sequential (“binary”) Sequential (“binary”) –Simple assignment Gray Gray –Assigns states by the minimum logic difference in the state transition graph. –I.e., assign adjacent codes to adjacent states –Reduces the amount of logic needed to decode each state. Johnson Johnson –Only one bit changes. One-hot One-hot –One bit in the state register for each state. –A large number of flip-flops, but no decoding for states. –Can result in smaller and faster FSMs, especially for ASICs with large amounts of sequential logic relative to combinational logic resources.

State Encoding (Example) NumberSequentialGrayJohnsonOne-Hot

State Diagram XX/0 00/1 0X/1 1X/1 0X/0 1X/0 XX/0 10/1 X1/

Circuit Implementation of FSM Combinational part Combinational part –compute next state and output given inputs and current state Sequential part Sequential part –use registers to store state codes –update state registers at each clock cycle

How to Describing a FSM and its circuit implementation in Verilog HDL?

Blocking and Non-blocking assignments “ <= “ : (non-blocking assignment): “ <= “ : (non-blocking assignment): –synchronized to clock (time unit) edge, concurrent = (blocking assignment): = (blocking assignment): –propagates immediately, sequential

Example: Blocking assignment “ = “ module swap; reg a, b, temp; (a or b) begin temp = a; a= b; b =temp; endendmodule

Example: Non-blocking assignment “ <= “ module swap; reg a, b; (a or b) begin a <= b; b <= a; endendmodule

intra and inter assignment #3 a <= b; a <= #3 b;

General Rules for Blocking and Non-blocking assignments <= (non-blocking assignment): synchronized to clock (time unit) edge, concurrent <= (non-blocking assignment): synchronized to clock (time unit) edge, concurrent = (blocking assignment):propagates immediately, sequential = (blocking assignment):propagates immediately, sequential # # (blocking delay) # RHS # RHS (non-blocking delay) Any of the four (2 X 2) possible combinations is allowed. Any of the four (2 X 2) possible combinations is allowed.

Example 1: module assign1; reg a,b,c,d; reg a,b,c,d; initial begin initial begin a = 0; b = 0; c = 0; d = 0; a = 0; b = 0; c = 0; d = 0; $monitor($time,,”a = %d, b =%d, c = %d, d = %d”, a,b,c,d); $monitor($time,,”a = %d, b =%d, c = %d, d = %d”, a,b,c,d); #20 $finish(2); #20 $finish(2); end end always begin always begin b = ~d; b = ~d; a = #2 b;//non-blocking delay c = ~c; #3 d <= c;//blocking delay end endendmodule

Example 2: module assign2; reg a, b, c, d; reg a, b, c, d; initial begin initial begin a = 0; b = 0; c = 0; d = 0; $monitor($time,,”a=%d, b=%d, c=%d, d=%d”,a,b,c,d); #20 $finish(2); end end always begin always begin b = ~b; #2 a = b;//blocking delay c = ~c; d <= #3 c;//non-blocking delay end endendmodule

Concurrent Execution clock) x = y; z = ~z;

HDL Coding Style for FSM Typically the synchronous portion is simply the state <= next_state assignment. Typically the synchronous portion is simply the state <= next_state assignment. The next_state portion is done in a purely combinational block (or multiple blocks). The next_state portion is done in a purely combinational block (or multiple blocks). –This is best done using a case statement rather than an if/else tree. –Defaults are easily set and excepted by unique cases.

FSM Verilog Behavior modeling Combinational part Combinational part (inputs or current states) begin case (current state) state1: next state =....; output = … ; output = … ; state2: … …end Sequential part Sequential part –cyclic behavior and edge detection –use non-blocking assignment for sequential behavior (posedge clk) begin current state <= next state; end

Generate CLOCK signal in Testbench module testbench; reg clk; parameter half_cycle = 50; initial begin clk = 0; … #350 $finish; end always begin #half_cycle clk = ~clk; endendmodule

Resets Using an asynchronous reset Using an asynchronous reset –Ensures that the state machine is always initialized to a known valid state. –No need to decode any unused current state values and thus minimizes next state logic. Using a synchronous reset or no reset Using a synchronous reset or no reset –Cannot predict initial state. –Must decode all states in the next state logic. –Can be a win if the next state logic is small compared to the additional size of the reset HW.

Assignment: Design a 4-bit counter with 1-bit input to control increase/decrease, 1 bit to reset to zero, and it should be synchronized. Design a 4-bit counter with 1-bit input to control increase/decrease, 1 bit to reset to zero, and it should be synchronized. –design the counter using FSM. Draw the state transition table/graph –design the counter using a while loop –design the counter using a for loop –design the counter using only if statement