AFE II Status

Analog Front-End (AFE) Board  Approximately 200 AFE boards are needed to readout CFT (&CPS/FPS) u 512 channel (2/cassette) u Analog output via SVX IIe u Discriminator output every 396 ns for L1 trigger u MultiChip module (MCM) s SIFT chip –Analog buffer to SVX –Discriminator output s SVX IIe

AFE II  A Tremendous Effort has already gone into AFE II PPD EE Department John Anderson Jim Hoff Abder Mekkaoui Paul Rubinov D0 Alan Bross Juan Estrada Carlos Garcia Peter Hasiakos Bruce Hoeneisen Marvin Johnson Mike Utes

AFE II  AFE II u Full New set of boards u No SIFT No SVX – Much simpler architecture u Will use instead s Trigger Pipeline Chip: TriP (or Tript - more in a bit) –Discriminators and analog pipeline –TriP chip submission was very successful – meets spec. s Commercial Flash ADCs + FPGA for analog information s Integrates completely with existing system u Will Have s No Front-end saturation problem –Reset once per crossing –Also allows for data taking in abort gap (cannot do presently with AFE I) VERY useful for Calibration studies s Improved Ped dispersion and stability –Lower and tighter threshold setting capability Channel by Channel - analog s Improved reliability s Improved readout flexibility –Decreased deadtime –Multi-buffering possible CFT Readout may dominate L1 readout rate without multi-buffering s Added Functionality with new submission of TriP Chip - Tript –z information from timing (  2 ns rms)

TriP  The existing TriP ASIC (7000 die on hand)  Lots of testing done over last 2 years

AFE II –TriP Performance  Measurements on TriP very promising u Noise at 1/5 pe rms u Threshold setting at 1.5 pe reliably u Very high quality Analog Data  Plot at right was obtained after 1 day of work on a TriP modified AFE board u To get this good, a plot with the AFE took about 1 month of dedicated work by the same people! s BLACK – DATA s RED – FIT  All Discriminators Firing!

AFE II – TriP Discriminator Performance  Upper plot u Red – all data u Blue same data with threshold and discriminator fires u Black – fit  Lower plot u Ratio of analog data with and without discriminator fires (threshold set)  47% occupancy

TriP-t: the new idea  About 1% additional components:(time to amplitude converter)  7 bits t-info offline: 120ns full scale=> 2ns time => ~30cm resolution in Z

AFE II - TriPt  With a rather simple modification to the TriP design – time stamp for hits can be obtained  Current TriP  Electronics resolution was determined to be  400 ps u For 8 pe signal expect about 2 ns sigma  Z measurement –  30 cm  Has impact on reco time and cluster splitting  In Z   +15 min bias MC s 40-60% reduction in reco time s D0 Note 4497 u Improvement in clustering algorithm utilizing z info also a possibility 400 ps intrinsic resolution

TriP-t prep work  Bench testing  New package

TriP-t current status  The chip designers are chip designing.  Ready for submission 23 Aug ’04  The new chip is the “critical path” item for the project  Some prep work going on now u We will need new packaging u We had some concerns about features used on the new chip, but not used on the old (current!) TriP chip, so we are retesting some things.

AFE II - Cost and Schedule  Full Project Plan Now Available

AFEII Prototype - current status  Schematic design is 100% complete.  Internal review was held in early May.  Layout of the board is about 95% complete.  All parts are here.  Req’s for boards are in the system.  RFQs for stuffing are on the street.  Firmware about 75% complete.

AFE II – Cost and Schedule  Cost M&S: u Production cost M&S are based on quotes for parts and labor – contingency estimate is grounds up:  Manpower u Estimates from AFE experience  Schedule critical path is the Tript chip  Completion for the 05 Shutdown is not likely  Planning for adiabatic Installation u AFE I and AFEII mixed running u Will need to test compatibility once AFE II prototypes are ready (9/04) u Installation will have to be done at the crate level (16 boards) because of difference in power requirements for AFE I and AFE II  Credibility of installation plan is dependent on prototype tests u How quickly they come up u Platform test and integration with trigger u Software readiness u Physical Installation can occur quickly (8 hour)

AFE II Milestones  AFE II Prototype under test9/04  Tript MOSIS submission9/04  D0 Internal Review1/05 u May be moved up to October  Director’s Review2/05 u May be moved up to Novemeber  Tript production submission3/05 u Possibility for “non-shared” submission in 12/04  AFE II pre-Production7/05 u Attempt to move up to 11/05 u Boards available for KEK Test?  AFE II production9/05  AFE II production complete12/05  First Board Ready for installation2/06

Conclusions – Improvements with AFE II  AFE II will u Improve noise floor and pedestal stability which will allow for consistent and reliable threshold setting with no discriminator feed-through or discriminator threshold shift s Will increase physics trigger efficiency s Potential for better hit efficiency and point resolution s Maintain capability of Preshower Detectors u No Front-End Saturation problem (reset once per crossing) u Added functionality of the Tript (z information) s Large reduction in reco time s Possible improvement in cluster finding –Cluster splitting leading to additional improvement in track quality u Readout architecture much more flexible s Less deadtime s Multiple buffers can be added to greatly increase L1 capability u Board construction is simpler, more robust s No MultiChip modules (MCM) s Mostly commercial parts/standard mounting techniques s Repairs/rework MUCH easier than in AFEI  AFEII will improve our capability to maintain high-quality and stable operation as the Tevatron Luminosity increases in RunII. This will allow D0 to maintain excellent tracking, trigger, and Preshower performance

DAQ System  We need to build a clone of the new test stand DAQ that is being put together at D0

New DAQ  Consists of(for 4 Board Readout) u VIPA crate (10U) s Bit3 controller s 1553 controller s VRB (VME readout bus) s VRBc (VRB controller) s Serial command link receiver card (SCLr) u Sequencer crate s Sequencer controler (SEQc) + SCLr s Sequencer s 2 fibers for connection of the VTM s 2 grey cables for connection to the AFEs (2AFEs/cable) u AFE s 4 (+2) Boards (minimum) s Two backplanes for cyostat. u PC and custom cables u Special trigger cards (2) (STDB) u Hardware for downloads of firmware for AFE, SEQ, VRBc, and SEQc

New DAQ  Cost (k$) u VME1 u SEQ1 u u Power supplies2 u AFE BPs2 u Bit3 controller1 u SEQc2 u AFEIIs4/each (X6) u SCLr cards2 u Rack1 u Cables, misc.4 TOTAL:  $40-50K

New DAQ  We have started work on the DAQ. However there is a great deal of work to do to have a system ready for the KEK test  There is also a VERY steep learning curve on becoming an expert on this system and at least one will be needed for the beam test. u So Far I have not been able to get additional Fermi people interested or, at least, committed to it (there is interest).