CPEN 315 - Digital System Design Chapter 9 – Computer Design C. Gerousis © Logic and Computer Design Fundamentals, 4rd Ed., Mano Prentice Hall Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc.

Overview Part 1 – Datapaths Part 2 – A Simple Computer Introduction Datapath Example Arithmetic Logic Unit (ALU) Shifter Datapath Representation and Control Word Part 2 – A Simple Computer Instruction Set Architecture (ISA) Single-Cycle Hardwired Control Part 3 – Multiple Cycle Hardwired Control Single Cycle Computer Issues Modifications to Datapath Modifications to Control Sequential Control Design

Introduction Computer Specification Instruction Set Architecture (ISA) - The parts of a processor's design that need to be understood in order to write a machine language instructions and registers – A low-level description. Computer Architecture - A high-level description of the hardware implementing the computer derived from the ISA. The architecture usually includes additional specifications such as speed, cost, and reliability.

Introduction (continued) Simple computer architecture decomposed into: Datapath for performing operations Control unit for controlling datapath operations A datapath is specified by: A set of registers The microoperations performed on the data stored in the registers A control interface

Datapaths Guiding principles for basic datapaths: The set of registers Collection of individual registers A set of registers with common access resources called a register file A combination of the above Microoperation implementation One or more shared resources for implementing microoperations Buses - shared transfer paths Arithmetic-Logic Unit (ALU) - shared resource for implementing arithmetic and logic microoperations Shifter - shared resource for implementing shift microoperations

Datapath Example Four parallel-load registers Load enable A select B select Write A address B address Four parallel-load registers Two mux-based register selectors Register destination decoder Mux B for external constant input Buses A and B with external address and data outputs ALU and Shifter with Mux F for output select Mux D for external data input Logic for generating status bits V, C, N, Z D data n Load R0 2 2 n n Load R1 n 1 MUX 2 n 3 1 Load MUX R2 2 3 n n Load R3 n n 1 2 3 n Register file Decoder D address A data B data 2 Constant in n n Destination select n 1 MB select MUX B Bus A n Address Bus B n Out Data A B n Out G select H select 4 A B 2 B S || C S V 2:0 in Arithmetic/logic I R Shifter I L C unit (ALU) G H N n n Z Zero Detect MF select 1 MUX F Function unit F n n Data In MD select 1 MUX D n Bus D

Datapath Example: Performing a Microoperation MD select 1 MUX D V C N Z n 2 A data B data Register file MUX B Address Out Data Bus A Bus B Function unit A B G select 4 Zero Detect MF select F MUX F H select S 2:0 || C in Arithmetic/logic unit (ALU) G Shifter H MUX 3 Decoder Load Load enable Write D data D address Destination select Constant in MB select A select A address B select B address R3 R2 R1 R0 Bus D Data In I L R Microoperation: R0 ← R1 + R2 Apply 1 to Load Enable to force the Load input to R0 to 1 so that R0 is loaded on the clock pulse (not shown) The overall microoperation requires 1 clock cycle Apply 0 to MF select and 0 to MD select to place the value of G onto BUS D Apply 01 to A select to place contents of R1 onto Bus A Apply 00 to Destination select to enable the Load input to R0 Apply 10 to B select to place contents of R2 onto B data and apply 0 to MB select to place B data on Bus B Apply 0010 to G select to perform addition G = Bus A + Bus B

Arithmetic Logic Unit (ALU) In this and the next section, we deal with design of typical ALUs and shifters Decompose the ALU into: An arithmetic circuit A logic circuit A selector to pick between the two circuits Arithmetic circuit design Decompose the arithmetic circuit into: An n-bit parallel adder A block of logic that selects four choices for the B input to the adder

Arithmetic Circuit Design (continued) There are only four functions of B to select as Y in G = A + Y + Cin: B input logic MUX n X C in Y out n-bit parallel adder S 1 A B A input Combinational

Logic Circuit * * Simplification could yield less complex logic.

Arithmetic Logic Unit (ALU) + 1 One stage of arithmetic circuit logic circuit 2-to-1 MUX S A B 2 G in For n-bit ALU the one stage circuit must be repeated n times.

ALU (continued) S2 = 0  Arithmetic operations S2 = 1  logic operations

Arithmetic Circuit Example Inputs Xi and Yi of each full adder in an arithmetic circuit have digital logic specified by the Boolean functions: Where S is a selection variable, Cin is the input carry, and Ai and Bi are input data for stage i. Draw the logic diagram for the 4-bit circuit using full-adders and multiplexers. Determine the arithmetic operation performed for each of the four combinations of S and Cin : 00, 01, 10 and 11.

4-Bit Basic Left/Right Shifter 3 I R L S Serial output L output R 2 1 H M U X Right shift fills position on left with value on input IR Serial outputs are available from serial output R. Shift Functions: (S1, S0) = 00 Pass B unchanged 01 Right shift 10 Left shift 11 Unused

Datapath Representation Address out Data out Constant in MB select Bus A Bus B FS V C N Z MD select n D data Write D address A address B address A data B data 2 m x Register file A B Function unit F 4 MUX B 1 MUX D Data in Earlier we looked at detailed design of ALU and shifter in the datapath Here we move up one level in the hierarchy from that datapath The registers, and the multiplexer, decoder, and enable hardware for accessing them become a register file The ALU, shifter, Mux F and status hardware become a function unit The remaining muxes and buses which handle data transfers are at the new level of the hierarchy

Datapath Representation (continued) Address out Data out Constant in MB select Bus A Bus B FS V C N Z MD select n D data Write D address A address B address A data B data 2 m x Register file A B Function unit F 4 MUX B 1 MUX D Data in In the register file: Multiplexer select inputs become A address and B address Decoder input becomes D address Multiplexer outputs become A data and B data Input data to the registers becomes D data Load enable becomes write The register file now appears like a memory based on clocked flip-flops (the clock is not shown) The function unit labeling is quite straightforward except for FS

Datapath Representation (continued) MD select 1 MUX D V C N Z n 2 A data B data Register file MUX B Address Out Data Bus A Bus B Function unit A B G select 4 Zero Detect MF select F MUX F H select S 2:0 || C in Arithmetic/logic unit (ALU) G Shifter H MUX 3 Decoder Load Load enable Write D data D address Destination select Constant in MB select A select A address B select B address R3 R2 R1 R0 Bus D Data In I L R Address out Data out Constant in MB select Bus A Bus B FS V C N Z MD select n D data Write D address A address B address A data B data 2 m x Register file A B Function unit F 4 MUX B 1 MUX D Data in Status Bits MF, G, and H must be defined in terms of the codes for FS

ALU Function Select (FS) S2 = 0  Arithmetic operations S2 = 1  logic operations

Definition of Function Unit Select (FS) Codes G Select, H Select, and MF in T of FS Codes FS(3:0) MF Select G Select(3:0) H Micr ooperation 0000 XX 0001 0010 0011 0100 0101 0110 0111 1000 1 X 00 1001 01 1010 10 1011 11 1100 XXXX 1101 1110 F A ¬ F A + B - F A A B Ù Ú sr sl Å

The Control Word The datapath has many control inputs The signals driving these inputs can be defined and organized into a control word To execute a microinstruction, we apply control word values for a clock cycle. For most microoperations, the positive edge of the clock cycle is needed to perform the register load The datapath control word format and the field definitions are shown next

The Control Word Fields A AA BA M B FS R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Fields DA – D Address AA – A Address BA – B Address MB – Mux B FS – Function Select MD – Mux D RW – Register Write The connections to datapath are shown in the next slide

Control Word Block Diagram AA BA M B FS R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R W Write D data 15 D A 14 D address 13 8 x n Register file 12 9 AA 11 A address B address 8 BA 10 7 A data B data n n n Constant in 1 MB 6 MUX B Bus A n Address out Bus B n Data out A B V 5 C Function 4 FS N unit 3 Z 2 n n Data in 1 MD 1 MUX D Bus D

Control Word Encoding Encoding of Control Word for Datapath F A 000 , AA, B MB FS MD R W Function Code 000 Register 0000 No write 1 001 Constant 0001 Data In Write 2 010 0010 3 011 0011 4 100 0100 5 101 0101 6 110 0110 7 111 0111 1000 1001 1010 1011 1100 1101 1110 F ¬ + - Ù Ú F B sr sl Å

Microoperations for the Datapath - Symbolic Representation W 1 2 3 e g ister unction Write 4 —* 6* 7 — Re gister Function Con s tant Func tio —— eg i t r N o Wr it Data in 5 – ¬ F A + + = l R6 sl 7 1 + 0 2 Data out ata in 5 0 Å *The shifter is driven by the B Bus  source for the shift is specified in the BA field rather than the AA field.

Control Word Example Given the sequence of 16-bit control words for the datapath and the initial ASCII character codes in 8-bit registers, simulate the datapath to determine the alphanumeric characters in the registers after the execution of the sequence. 011 011 001 0 0010 0 1 R0 00000000 100 100 001 0 1001 0 1 R1 00100000 101 101 001 0 1010 0 1 R2 01000100 001 001 000 0 1011 0 1 R3 01000111 001 001 000 0 0001 0 1 R4 01010100 110 110 001 0 0101 0 1 R5 01001100 111 111 001 0 0101 0 1 R6 01000001 011 111 000 0 0000 0 1 R7 01001001 MD = 0  Function MB = 0  Function RW = 1  Write

Control Word Example (continued) AA BA M B FS R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 10 8 14 13 11 Bus D Constant in n MUX B 1 D data Write D address A address B address A data B data x Register file A B Function unit MUX D Data in Bus A Bus B R W 12 AA 15 D BA 9 Address out Data out V C N Z 7 MD MB 6 4 FS 5 3 2 011 011 001 0 0010 0 1 R3 R1 Addition R3 01000111 R1 00100000

Control Word Example (continued)

Control Word Example (continued) 100 100 001 0 1001 0 1 001 001 000 0 0001 0 1 R1 00100000 R4 01010100 ‘t’ 110 110 001 0 0101 0 1 R6 01000001 ‘a’ 101 101 001 0 1010 0 1 R1 00100000 R5 01001100 ‘l’ 111 111 001 0 0101 0 1 R7 01001001 ‘i’ 001 001 000 0 1011 0 1 011 111 000 0 0000 0 1 ‘i’ D i g i t a l