Defocus-Aware Leakage Estimation and Control Andrew B. Kahng †‡ Swamy Muddu ‡ Puneet Sharma ‡ CSE † and ECE ‡ Departments, UC San Diego

Outline ► Systematic Components of Linewidth Variation ► Defocus-Aware Leakage Estimation ► Experimental Study ► Defocus-Aware Leakage Optimization ► Summary

Leakage Power ► Leakage power limits large, high-performance designs in sub-100nm regime ► Decreasing threshold voltages (V th ) boost performance but increase leakage ► Components of leakage power  Subthreshold leakage  Gate leakage  Band-to-band tunneling leakage Subthreshold leakage is a substantial component of total leakage power through the 65nm node ► Leakage variability is another concern  Small variation in linewidth  exponential variation in leakage power ► Most significant source of leakage variability : linewidth variation  E.g., in 90nm technology, decrease of linewidth by 10nm  leakage increases by 5X for PMOS and 2.5X for NMOS

Linewidth Variation ► Traditional leakage estimation techniques model linewidth variation as random  very pessimistic ► Reality: Linewidth variation is partly systematic! ► This work: (1) analyze impact of focus variations  (2) improve leakage estimation accuracy  (3) optimize leakage accurately  (4) reduce pessimistic guardbanding Bossung plot

Optical Proximity Correction (OPC) OpticalModels OPC Standard cell layout Optical models with focus/exposure conditions OPC’ed layout Focus Exposure Process window  OPC solution valid OPC solution not valid outside process window

Linewidth Variation with Focus Standard cell OPC at nominal defocus Lithography simulation at nominal defocus Lithography simulation at 200nm defocus Printed polysilicon line in yellow shows SIGNIFICANT deviation from drawn for 200nm defocus Printed polysilicon line in yellow shows NO deviation from drawn for nominal defocus

Sources of Focus Variation ► Defocus during lithography is caused primarily due to wafer topography variation, lens aberration and wafer plane tilt  Blurring caused by defocus results in lower image resolution, improper resist development, and linewidth variation ► Wafer topography variation is caused due to chemical- mechanical polishing (CMP) and shallow trench isolation (STI) fill anomalies during wafer processing  Substrate flatness, films, etc. also contribute to wafer topography Imperfect wafer planarity after STI CMP Images print at different defocus levels depending on the topography of the location

Through-Focus Linewidth Variation ► Linewidth variation due to line pitch (  “through- pitch”) is compensated by OPC at nominal defocus  At defocus levels other than nominal, linewidth varies systematically with pitch  Dense pitch: high density of features within optical radius  Isolated pitch: low density of features within optical radius  Linewidth for dense pitches increases with defocus  “smiling”  Linewidth for isolated pitches decreases with defocus  “frowning” ► Linewidth variation with pitch and defocus is captured in Bossung lookup tables  At any given defocus level, linewidth for dense pitches is always greater than that of isolated pitches

Isolated vs. Dense Linewidth Variation Portion of a 90nm standard cell layout showing polysilicon lines in isolated, dense and self- compensated contexts Dense lines  “smiling” (linewidth > nominal) Isolated lines  “frowning” (linewidth < nominal) Self-compensated lines  (linewidth ~ nominal)

Outline ► Systematic Components of Linewidth Variation ► Defocus-Aware Leakage Estimation ► Experimental Study ► Defocus-Aware Leakage Optimization ► Summary

Defocus-Aware Leakage Estimation Flow ► Core idea: Layout analysis  Defocus-aware linewidth prediction  leakage estimation ► Flow components  Bossung LUT creation  Pitch calculation  Cell leakage estimation Layout AnalysisPlaced Design Device PitchesDefocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation Layout AnalysisPlaced Design Device PitchesDefocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation Layout Analysis Placed Design Device Pitches Defocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation

Bossung Lookup Table Creation ► Done once for a given lithography optical model ► Line-and-space patterns to simulate different line pitches ► Lithography simulation performed in (-200,200)nm defocus range with 0.38 exposure dose and 0.7 numerical aperture ► Table Rows: pattern information ► Table Columns: defocus level ► Table Entries: printed linewidths Layout AnalysisPlaced Design Device PitchesDefocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation Layout AnalysisPlaced Design Device PitchesDefocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation Layout Analysis Placed Design Device Pitches Defocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation

Pitch Calculation ► Device pitch calculation is done using  Location and orientation of standard cells  Device locations within each cell from LVS ► Device pitch and optical radius used to lookup line- and-space patterns in Bossung table Layout AnalysisPlaced Design Device PitchesDefocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation Layout AnalysisPlaced Design Device PitchesDefocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation Layout Analysis Placed Design Device Pitches Defocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation

Cell Leakage Estimation ► Cell leakage estimation  Cell leakage for each input state estimated by finding leaking devices by logic simulation ► Leakage of stacked devices is neglected  Cell leakage computed using pre-characterized PMOS and NMOS leakage tables generated from SPICE simulation  Estimate is within 5% of cell-level SPICE simulation Layout AnalysisPlaced Design Device PitchesDefocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation Layout AnalysisPlaced Design Device PitchesDefocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation Layout Analysis Placed Design Device Pitches Defocus over Die CMP Simulation Bossung Lookup Table Predicted Linewidths Leakage Estimation

Outline ► Systematic Components of Linewidth Variation ► Defocus-Aware Leakage Estimation ► Experimental Study ► Defocus-Aware Leakage Optimization ► Summary

Experimental Setup ► Testcases: c5315 (2077 cells), c6288 (4776 cells), c7552 (3155 cells), alu128 (11724 cells) ► Cell library (20 cell) characterization with BPTM BSIM3 device models, Synopsys HSPICE, and Cadence SignalStorm ► Synthesis with Synopsys Design Compiler with tight delay constraints. Placement with Cadence SoC Encounter. ► OPC, litho-simulation and scattering-bar insertion with Mentor Calibre using industry-strength recipes for 100nm linewidth and 193nm stepper. ► Topography used: +100nm at die center, quadratically decreases to -100nm at die corners

Leakage Estimation Results Spread Reduction c5315: 56% c7552: 49% c6288: 49% alu128: 62% WC: Worst Case BC: Best Case DATO: Defocus-Aware, Topography-Oblivious Defocus Gaussian random with µ=0nm, 3σ=200nm DATA: Defocus-Aware, Topography-Aware Defocus Gaussian random with µ=predicted topography height 3σ=100nm

Per-Instance Leakage Estimation ► Ability to predict leakage for each cell instance Error distribution of traditional leakage estimation for c6288 at nominal process corner  Can drive leakage reduction techniques like V th assignment, input vector control, gate-length biasing E.g., optimize cells that are more leaky (Negative error  Traditional estimate is higher)

Outline ► Systematic Components of Linewidth Variation ► Defocus-Aware Leakage Estimation ► Experimental Study ► Defocus-Aware Leakage Optimization ► Summary

Gate-Length Biasing (Gupta et al. DAC04) ► Slightly increase (bias) the gate-length (linewidth) of devices  Slightly increases delay  Significantly reduces leakage  Bias only the non-critical devices ► Advantages:  Reduces runtime leakage and leakage variability  Can work in conjunction w/ V th assignment  Gives finer control over delay-leakage tradeoff  Post-layout technique, no additional masks required ► 15-40% leakage and 30-60% leakage variability reduction for 90nm with dual-V th assignment ► We add defocus-awareness to gate-length biasing

Defocus-Aware Gate-Length Biasing ► Sensitivity-based greedy opt. in gate-length biasing Sensitivity of cell p = ξ p = ΔL p ×s p ΔL p : Leakage reduction of cell p upon biasing s p : Timing slack of cell p after biasing it ► Defocus aware sensitivity function: ξ p = ‹ΔL p ›×s p ‹ΔL p › : Expected leakage reduction of cell p ► Expected leakage reduction computation: ‹ΔL p › = ∑ t ‹ΔL pt › ‹ΔL pt › : Exp. leakage reduction of device t of cell p Δ L pt = f( l pt ) l pt : gate-length l pt = g(D pt, P pt ) D pt : defocus; P pt : pitch ‹ΔL pt › = ∑ t ∑ D f(g(D pt, P pt )). P (D pt ) P : probability defocus is D pt ► We assume defocus (D) to be Gaussian random  Topography-oblivious: µ=0nm, 3  =200nm  Topography-aware: µ=topography height, 3  =100nm

Results Leakage after traditional and defocus-aware gate-length biasing ► Optimization for nominal corner and topography mentioned earlier ► Modest leakage reductions from 2-7% ► 10% optimization runtime increase

Summary ► Conclusions:  Super-linear dependence of leakage on linewidth  pessimism in linewidth  large leakage estimation pessimism  Proposed approach models pitch- and defocus-dependent systematic variations.  Significant reduction in leakage estimation spread observed.  Improved per-instance leakage estimation  use in leakage reduction approaches.  Defocus awareness in gate-length biasing improves leakage reduction by 2-7%. ► Future Work  Include other sources of systematic variation like lens aberrations.  Consider systematic impact on timing also while optimization.

Thank You! Questions?