Topography-Aware OPC for Better DOF margin and CD control Puneet Gupta, Andrew B. Kahng†‡, Chul-Hong Park†, Kambiz Samadi†, and Xu Xu‡ * Blaze-DFM Inc.

Slides:

Advertisements

Similar presentations

Hierarchical Dummy Fill for Process Uniformity Supported by Cadence Design Systems, Inc. NSF, and the Packard Foundation Y. Chen, A. B. Kahng, G. Robins,

Advertisements

Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.

A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.

Efficient Design and Analysis of Robust Power Distribution Meshes Puneet Gupta Blaze DFM Inc. Andrew B. Kahng.

Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng 1 Ion I. Mandoiu 2 Qinke Wang 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department, University.

Ahmed Awad Atsushi Takahash Satoshi Tanakay Chikaaki Kodamay ICCAD’14

Dual Graph-Based Hot Spot Detection Andrew B. Kahng 1 Chul-Hong Park 2 Xu Xu 1 (1) Blaze DFM, Inc. (2) ECE, University of California at San Diego.

Background: Scan-Based Delay Fault Testing Sequentially apply initialization, launch test vector pairs that differ by 1-bit shift A vector pair induces.

Puneet Sharma and Puneet Gupta Prof. Andrew B. Kahng Prof. Dennis Sylvester System-Level Living Roadmap Annual Review, Sept Basic Ideas Gate-length.

Detailed Placement for Improved Depth of Focus and CD Control Puneet Gupta 1 Andrew B. Kahng 1,2 Chul-Hong Park 2 1 Blaze DFM,

Multi-Project Reticle Design & Wafer Dicing under Uncertain Demand Andrew B Kahng, UC San Diego Ion Mandoiu, University of Connecticut Xu Xu, UC San Diego.

Power-Aware Placement

WaferReticle Project Yield-Driven Multi-Project Reticle Design and Wafer Dicing Andrew B. Kahng 1, Ion Mandoiu 2, Xu Xu 1, and Alex Z. Zelikovsky 3 1.

UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.

Reticle Floorplanning With Guaranteed Yield for Multi-Project Wafers Andrew B. Kahng ECE and CSE Dept. University of California San Diego Sherief Reda.

Performance-Impact Limited Area Fill Synthesis

Design Sensitivities to Variability: Extrapolations and Assessments in Nanometer VLSI Y. Kevin Cao *, Puneet Gupta +, Andrew Kahng +, Dennis Sylvester.

Architectural-Level Prediction of Interconnect Wirelength and Fanout Kwangok Jeong, Andrew B. Kahng and Kambiz Samadi UCSD VLSI CAD Laboratory

Enhanced Resist and Etch CD Control by Design Perturbation Abstract Etch dummy features are used to reduce CD skew between resist and etch processes and.

Supply Voltage Degradation Aware Analytical Placement Andrew B. Kahng, Bao Liu and Qinke Wang UCSD CSE Department {abk, bliu,

Study of Floating Fill Impact on Interconnect Capacitance Andrew B. Kahng Kambiz Samadi Puneet Sharma CSE and ECE Departments University of California,

Detailed Placement for Improved Depth of Focus and CD Control

On Legalization of Row-Based Placements Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La Jolla, CA 92093

Practical Iterated Fill Synthesis for CMP Uniformity Supported by Cadence Design Systems, Inc. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky (UCLA, UVA.

Fast and Area-Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts Charles Chiang, Synopsys Andrew B. Kahng, UC San Diego Subarna.

UC San Diego Computer Engineering. VLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD.

April 16th, Photomask Japan 2008 Electrical Metrics for Lithographic Line-End Tapering Puneet Gupta 3,

Chung-Kuan Cheng†, Andrew B. Kahng†‡,

DPIMM-03 1 Performance-Impact Limited Area Fill Synthesis Yu Chen, Puneet Gupta, Andrew B. Kahng (UCLA, UCSD) Supported by Cadence.

On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.

1 UCSD VLSI CAD Laboratory ISQED-2009 Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization Kwangok Jeong, Andrew.

Toward Performance-Driven Reduction of the Cost of RET-Based Lithography Control Dennis Sylvester Jie Yang (Univ. of Michigan,

Fill for Shallow Trench Isolation CMP Andrew B. Kahng 1,2 Puneet Sharma 1 Alexander Zelikovsky 3 1 ECE Department, University of California – San Diego.

Design Bright-Field AAPSM Conflict Detection and Correction C. Chiang, Synopsys A. Kahng, UC San Diego S. Sinha, Synopsys X. Xu, UC San Diego A. Zelikovsky,

UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.

A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools.

Toward a Methodology for Manufacturability-Driven Design Rule Exploration Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, and Jie Yang.

Detailed Placement for Leakage Reduction Using Systematic Through-Pitch Variation Andrew B. Kahng †‡ Swamy Muddu ‡ Puneet Sharma ‡ CSE † and ECE ‡ Departments,

Defocus-Aware Leakage Estimation and Control Andrew B. Kahng †‡ Swamy Muddu ‡ Puneet Sharma ‡ CSE † and ECE ‡ Departments, UC San Diego.

Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing Puneet Gupta 1 Andrew B. Kahng 1,2,3 O.S. Nakagawa 1 Kambiz.

Design of Integrated-Circuit Interconnects with Accurate Modeling of Chemical-Mechanical Planarization Lei He, Andrew B. Kahng* #, Kingho Tam, Jinjun Xiong.

UC San Diego Computer Engineering. VLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD.

Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control Puneet Gupta 1 Andrew B. Kahng 1 Puneet Sharma 1 Dennis Sylvester 2 1 ECE Department,

Hierarchical Dummy Fill for Process Uniformity Supported by Cadence Design Systems, Inc. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky (UCLA, UCSD, UVA.

7/14/ Design for Manufacturability Prof. Shiyan Hu Office: EERC 731.

1 A Novel Metric for Interconnect Architecture Performance Parthasarathi Dasgupta, Andrew B. Kahng, Swamy V. Muddu Dept. of CSE and ECE University of California,

UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.

Dose Map and Placement Co-Optimization for Timing Yield Enhancement and Leakage Power Reduction Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong.

Accuracy-Configurable Adder for Approximate Arithmetic Designs

Hongbo Zhang, Yuelin Du, Martin D.F. Wong, Yunfei Deng, Pawitter Mangat Synopsys Inc., USA Dept. of ECE, Univ. of Illinois at Urbana-Champaign GlobalFoundries.

Seongbo Shim, Yoojong Lee, and Youngsoo Shin Lithographic Defect Aware Placement Using Compact Standard Cells Without Inter-Cell Margin.

1 SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects Qiang Xu and Yubin Zhang Krishnendu Chakrabarty The Chinese.

Number of Blocks per Pole Diego Arbelaez. Option – Number of Blocks per Pole Required magnetic field tolerance of ~10 -4 For a single gap this can be.

UC San Diego / VLSI CAD Laboratory Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop Insertion Andrew B. Kahng, Ilgweon Kang and Siddhartha Nath.

Kwangsoo Han, Andrew B. Kahng, Hyein Lee and Lutong Wang

Kwangsoo Han‡, Andrew B. Kahng‡† and Hyein Lee‡

Closing the Smoothness and Uniformity Gap in Area Fill Synthesis Supported by Cadence Design Systems, Inc., NSF, the Packard Foundation, and State of Georgia’s.

 Chemical-Mechanical Polishing (CMP)  Rotating pad polishes each layer on wafers to achieve planarized surfaces  Uneven features cause polishing pad.

Pattern Sensitive Placement For Manufacturability Shiyan Hu, Jiang Hu Department of Electrical and Computer Engineering Texas A&M University College Station,

Pattern Sensitive Placement For Manufacturability Shiyan Hu, Jiang Hu Department of Electrical and Computer Engineering Texas A&M University College Station,

NUMERICAL TECHNOLOGIES, INC. Assessing Technology tradeoffs for 65nm logic circuits D Pramanik, M Cote, K Beaudette Numerical Technologies Inc Valery Axelrad.

LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits H. Yao, Y. Cai and Q. Gao EDA Lab, Department of CS, Tsinghua University,

Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes Sorin Dobre +, Andrew B. Kahng * and Jiajia Li * * UC San Diego VLSI CAD.

Xiaoqing Xu1, Tetsuaki Matsunawa2

1 Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs Zhi-Wen Lin and Yao-Wen Chang National Taiwan University.

Date of download: 9/20/2016 Copyright © 2016 SPIE. All rights reserved. Top view of the studied mask and the splitting strategy for the investigated LELE.

Capacitance variation 3/ (%)

Revisiting and Bounding the Benefit From 3D Integration

Lithography Advanced.

Presentation transcript:

Topography-Aware OPC for Better DOF margin and CD control Puneet Gupta*, Andrew B. Kahng*†‡, Chul-Hong Park†, Kambiz Samadi†, and Xu Xu‡ * Blaze-DFM Inc. † ECE Dept. University of California, San Diego ‡ CSE Dept. University of California, San Diego

Motivation The depth-of-focus variation corresponding to thickness variation severely affects the metal patterning of the subsequent upper layer Standard OPC (SOPC) assigns zero defocus for each layer which will lead to CD variation of the metal feature that will be placed on that layer Topography-aware OPC (TOPC) will compensate for thickness variation and will adjust the OPC and ORC accordingly

(a) Side view showing thickness variation over regions with dense and sparse layout. (b) Top view showing CD variation when a line is patterned over a region with uneven wafer topography, i.e., under conditions of varying defocus. CD variation by topography New OPC technique that is aware of post-CMP topography variation is required

(a)Original layout and simulation result with zero DOF model (b)Original layout and simulation result with -0.3um DOF model in the non-planar topography (c)Standard OPC layout and simulation result with zero defocus model (d)Standard OPC layout and simulation result with -0.3um DOF model in the non-planar topography SOPC Simulation Results (c) (d) Original metal OPC layer Resist Image (b) -0.3 DOF 0.0 DOF -0.3 DOF 0.0 DOF (a) SOPC cannot compensate CD variation induced by topography!!

Standard vs. Topography-Aware OPC and ORC OPC Method ORC Method ∆CD (Drawn vs. Printed) STD 00 T-A> 0 T-ASTD> 0 T-A 00 The following table shows four different combinations of OPC and ORC (STD, and T-A stands for Standard and Topography- aware methodologies, respectively) STD OPC/ORC will generate a small CD error, but the premise of this method is at fault STD-OPC/T-A-ORC combination yields a large CD error and hence not desirable. T-A-OPC/STD-ORC combination does not make sense! T-A-OPC/T-A-ORC yields a small CD error and considers layers with uneven topography

K-DML Assignment Problem Always try to assign one feature to DML partition according to its height However, assign two features within the distance of R to different DML Partition will result in Optical Error Objective: Partition of all features into k DMLs to minimize the number of optical errors Assignment according to height Distance < R Modified Assignment

k-DML Assignment Algorithm Compute the post-CMP topography and the height for each feature Construct a network flow topology with vertex v for each feature and an edge between two close vertices for (i = 1; i < k; i++) Calculate edge capacitances Solve the maximum S-T flow problem All vertices on the S side of the cut are assigned to DML i ST 1 10 Max flow =1  Min cut =1

A map of thickness variation from CMP simulation is converted to DML and then fed into GDSII for TOPC TOPC applies different DOF models to metal lines according to DML TOPC Flow CMP Simulation DOF Marking Layer Library & Technology GDSII Input GDSII for TOPC TOPCed GDSII DOF Model Database TOPC SOPC SOPCed GDSII Standard OPC Flow

Experimental Setup Sigma-C’s Solid-C –Check CD of metals on topography Mentor’s OPCpro –TOPC, SOPC and ORC (Optical Rule Check) Cadence SOC Encounter –Placement & Route Synopsys Design Complier –Synthesis

DOF Enhancement Evaluate DOF margin at a test pattern –TOPC enhances DOF margin as topography thickness has over 0.2µm –Total DOF range of TOPC at 0.2um is increased by 0.14um compared to SOPC Test pattern : 0.14µm W/ 0.9µm S 0.9 Topography: thickness (µm) Method SOPC directional DOF range (µm) directional DOF range (µm) TOPC

EPE Reduction DML CASE I DOF ( µ m) TOPC ( µ m) CASE II DOF ( µ m) TORC ( µ m) DML TOPC ( µ m) TORC ( µ m) EPE is evaluated by alu128 testbed from Artisan TSMC 0.09 µ m CASE I: assume the stepper machine focuses on the average of the topography ( Focus on DML1 ) CASE II: assume the stepper machine focuses on DML2

Conclusions and Ongoing works Conclusions –The novel methodology for wafer-topography aware OPC is proposed –For 90nm foundry library, TOPC achieves up to 75% reduction of EPE at worst-case defocus Ongoing works –Investigate the impact of a CD error reduction on RC parasitics of the circuit –Study new DML assignment to reduce the CD error at boundary of DMLs Testcas e SOPCTOPCImprovement (%) Case I Case II