- Frédéric Druillole - Présentation du SEDI 1 30/06/2015 Complete electronic Readout for Active Target (CERAT) Project Project Physicist’s demands Physicist’s demands Technical aspects Technical aspects

30/06/ Frédéric Druillole - Présentation du SEDI 2 Project GOAL: Definitioneeds Definition of the needs Feasibility Study Feasibility Study To propose an organization To propose an organization Critical points to list Critical points to list Mock-up to define Mock-up to define Constraint :  « We want to use an ASIC based on AFTER circuit»

30/06/ Frédéric Druillole - Présentation du SEDI 3 Phase A organization Detector A – Experiment A Detector B – Experiment B Detector C – Experiment C Detector D – Experiment D Physic specification Detector Specification Physic specification Detector Specification Physic specification Detector Specification Physic specification Detector Specification Technical Manager Scientific Manager System Engineer µElectronic Engineer Digital electronic Engineer Software Engineer SystemGroup CONCEPTUALDESIGNREPORT

30/06/ Frédéric Druillole - Présentation du SEDI 4 System Information Needs For each detector, we need information to conceive a system:For each detector, we need information to conceive a system: –Physic information –Detector Information –System Information Demands are different than the AFTER+ requirement. It is a view of the whole system which is asked.  Excell File to fill up: SizeSystem.xls SizeSystem.xls Exemple of the CENBG detector --- > ---

30/06/ Frédéric Druillole - Présentation du SEDI 5 Excell File: CENBG AFTER + Interest domain from CENBG New detector 20 cm x 20 cm, 2mm granularity→ pads Negative polarity Min threshold value ≈ 1fC Input dynamic range 1fC-1pC DNL ≈ 1% Time observation ≈ 10 μs Dead time < 1ms ≈ 1000 pads fired/event Ideal number of channels/chip = 128

30/06/ Frédéric Druillole - Présentation du SEDI 6 T2K Readout system Pre-amp and shapers Samplers and analog memory buffers Analog to digital conversion Digital buffer Data concentration ~ channels 1728 Front end ASICs On-detector electronics 72 Optical fibers 1-6 Tbaud*/s peak *1 baud = 10 bit ~2 ms retention max. 34 Gbaud/s peak 400 Gbit/s peak ~1-10 Gbit/s averaged Shared DAQ system ~0.1-1 Gbit/s Standard LAN connection(s) 432 Front end cards 72 Mezzanines Off-detector electronics

30/06/ Frédéric Druillole - Présentation du SEDI 7 Potential ACTAR Readout system Pre-amp and shapers Samplers and analog memory buffers Analog to digital conversion Digital buffer Data concentration ~ channels 139 Front end ASICs On-detector electronics 6 Optical fibers *1 baud = 10 bit ~2 ms retention max. 3 Gbaud/s peak 40 Gbit/s peak ~1-10 Gbit/s averaged Shared DAQ system ~0.1-1 Gbit/s Standard LAN connection(s) 35 Front end cards 6 Mezzanines Off-detector electronics Do we need an external DCC ?

30/06/ Frédéric Druillole - Présentation du SEDI 8 A DAQ LOGIC RTOS Mémoire SDRAM (64 MB) Mémoire Flash (4 MB) boot / local system file Processeur (Motorola Slow Control Slow control task Slow control of the floor Ethernet Link (100Mbit/s or GigaBit) Off the detector Data Task Data Data of a detection node (ASIC + ADC) Programmable Logic Programmable Logic FPGA (1M gates)

30/06/ Frédéric Druillole - Présentation du SEDI 9 Data Stream (hight speed) (FPGA) Multiplexeur Buffer RAM Data from ASIC + Filter + Compression +N Channels Comptage Channel 1 Channel 2 Comptage AFTER 0 AFTER 1 AFTER 0 AFTER 5 AFTE R 1 AFTER 2 ARS 3 AFTER 4 Processor 100 Mb/s Ethernet Port N ms Data To Off Detector N ms Periodical slow control/configuration Experiment clock Slow control Object In ANTARES, we reach 350kBq with an event size of 6 bytes

30/06/ Frédéric Druillole - Présentation du SEDI 10 Annexes : Functions Shared DAQ system Pre-amp and shapers Samplers and analog memory buffers Analog to digital conversion Digital buffer Data concentration Pre-amp and shapers Samplers and analog memory buffers Analog to digital conversion Digital buffer Data concentration Pre-amp and shapers Samplers and analog memory buffers Analog to digital conversion Digital buffer Data concentration Pre-amp and shapers Samplers and analog memory buffers Analog to digital conversion Digital buffer Data concentration Pre-amp and shapers Samplers and analog memory buffers Analog to digital conversion Digital buffer Data concentration Pre-amp and shapers Samplers and analog memory buffers Analog to digital conversion Digital buffer Data concentration Trigger level 1 (multiplicity) Global Trigger N detectors Ancilliary detectors Ancilliary detectors Ancilliary detectors Ancilliary detectors Global clock GPS What resolution FEM to FEM ? What resolution channel per channel ?

30/06/ Frédéric Druillole - Présentation du SEDI 11 Conclusion We plan to have a brainstorming meeting in few weeks : –(perhaps in Bordeaux) Actar collaboration must designate –Scientific Manager : (E. Pollacco) –Techncal Manager : (JL Pedroza) Actar : writing the CDR by the end of the year ? Cost Model from info we will got (Excell File). Agreed to fill up the file ?