Group M3 Nick Marwaha Craig LeVan Jacob Thomas Darren Shultz Project Manager: Zachary Menegakis February 28, 2005 MILESTONE 7 Component Layout DSP 'Swiss Army Knife' Overall Project Objective: General Purpose Digital Signal Processing Chip

STATUS Design Proposal (Done) Architecture (Done) Size Estimates/Floorplan/Verilog (95%) Gate Level Design (99%) Component Layout (Done) Functional Block (50%) To Be Done Complete layout of functional blocks Wallace Tree Multiplier, etc. Layout of Adder and div remain Schematic Make remaining adjustments for comb/Wallace Top-level Verification Test adjusted blocks

DESIGN DECISIONS Layout Re-did XOR and FA (and others) using M2 to reduce size Going to need all four layers for the fp_mult Not a big issue because we don’t route over them Wallace Tree Multiplier Fully implemented booth encoding All blocks for wallace tree done to conform to aspect ratio

MENTAL BREAK

OLD WALLACE TREE

NEW WALLACE TREE

Wallace Tree Mult

Booth Encoding – PP_Gen

TRANSISTOR COUNT

LAYOUT UPDATE - FA

LAYOUT UPDATE REG BOOTH DECODER

LAYOUT UPDATE 3:2 COMPRESSOR COMPARATOR

FLOORPLAN BEFORE

FLOORPLAN AFTER

UPDATE – TEXT VERSION Since 3pm: Craig – Worked on Booth Recoding and floorplan Darren – Got in a car… Jake – Worked on layout (only 13hrs straight this time) Nick – ditto

PROBLEMS & QUESTIONS Booth Recoding Still walking through Problem: Timing issues with top level design. Haven’t tackled yet (fixing lower blocks to avoid complications*) Problem: Spring break We want one * scientific method: only test one variable at a time