Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.

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Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout

Recall the !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0

Edge-triggered D Flip-flop

D Flip-Flop CLK DQ !Q X 0 Q 0 !Q 0 D CLK Q !Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

Each Xilinx macrocell contains a D flip-flop Controlled inverter

Each Xilinx macrocell contains a D flip-flop Note asynchronous preset x Q.AP = x Note asynchronous reset Q.AR = y y Q.D = z z

Divide-by-2 Counter CLK Q0 Q0.D = !Q0 CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0

MODULE div2cnt TITLE 'Divide By 2 Counter' DECLARATIONS " INPUT PINS " PB PIN 70; " push-button switch (clock) " OUTPUT PINS " Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16 div2cnt.abl CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0 Registered Buffer output

EQUATIONS Q0.C = PB; Q0.D = !Q0; test_vectors(PB -> Q0).C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0; END div2cnt.abl (cont’d) CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0.C. means clock goes LO-HI-LO Power-on output Q0 = 0

A 1-Bit Register

A 4-Bit Register

J-K Flip-flops Q.D = J & !Q # !K & Q

J-K Flip-flops

T Flip-flops Q.D = T $ Q

T Flip-flops

MODULE Tdiv2cnt TITLE 'Divide By 2 Counter using T flip-flop' DECLARATIONS " INPUT PINS " PB PIN 70; " push-button switch (clock) " OUTPUT PINS " Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16 EQUATIONS Q0.C = PB; Q0.T = 1; test_vectors(PB -> Q0).C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0; END 1