Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 6 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Dynamic Power: Device Sizing Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 62 Delay of a CMOS Gate CMOS gate CLCL CgCg C int Propagation delay through the gate: t p = 0.69 R eq (C int + C L ) ≈ 0.69 R eq C g (1 + C L /C g ), C int ≈ C g = t p0 (1 + C L /C g ) t p0 = intrinsic or unloaded delay Gate capacitance Intrinsic capacitance

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 63 R eq, C g, C int, and Width Sizing Sizing: Keep L fixed, increase W by size factor S Sizing: Keep L fixed, increase W by size factor S R eq : equivalent resistance of “on” transistor for standard gate, proportional to L / W; R eq : equivalent resistance of “on” transistor for standard gate, proportional to L / W; reduces to R eq / S C g : standard gate capacitance, proportional to C ox WL; C g : standard gate capacitance, proportional to C ox WL; increases to SC g C int : intrinsic output capacitance, for submicron processes C int : intrinsic output capacitance ≈ C g, for submicron processes t p0 : intrinsic delay = 0.69R eq C g ; t p0 : intrinsic delay = 0.69R eq C g ; remains unchanged with sizing – is purely a function of the technology

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 64 Delay of a Gate Sized by Factor S t p =0.69 R eq /S (SC g + C L ) =0.69 R eq C g (1 + C L /SC g ) =t p0 (1 + C L /SC g ) Intrinsic delay of standard gate in technology Ratio of load capacitance to capacitance of sized gate

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 65 Effective Fan-out, F Effective fan-out is defined as the ratio of the external load capacitance to the standard gate capacitance: Effective fan-out is defined as the ratio of the external load capacitance to the standard gate capacitance: F=C L /C g t p = t p = t p0 (1 + C L /C g ) =t p0 (1 + F )

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 66 Sizing an Inverter Chain Cg1Cg1 Cg2Cg2 CLCL #1 (standard) #2 (size f2)#N (size fN) C g2 = f2C g1 t p1 = t p0 (1 + C g2 /C g1 ) t p2 = t p0 (1 + C g3 /C g2 )N t p =Σ t pj =t p0 Σ (1 + C gj+1 /C gj ) j =1j=1

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 67 Minimum Delay Sizing Equate partial derivatives of t p with respect to C gj, j = 2, 3,..., to 0: 1/C g1 – C g3 /C g2 2 = 0, etc. or C g2 2 = C g1 ×C g3, etc. or C g2 /C g1 = C g3 /C g2, etc. i.e., all stages are sized up by the same factor f with respect to the preceding stage: C L /C g1 = F = f N, t p = Nt p0 (1 + F 1/N )

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 68 Minimum Delay Sizing Equate partial derivatives of t p with respect to N to 0: dNt p0 (1 + F 1/N ) ───────── = 0 dN i.e. F 1/N – F 1/N (ln F)/N = 0 or ln f = 1 → f = e = and N = ln F

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 69 Delays of Loaded Gates F = fan-out factor F = fan-out factor Single stage, no sizing Single stage, no sizing t = t (1 + F) t p = t p0 (1 + F) Two-stage optimum sizing Two-stage optimum sizing t = 2t (1 + √F) t p = 2t p0 (1 + √F) N = ln F stage optimum sizing N = ln F stage optimum sizing t = t ln F (1 + N √F) t p = t p0 ln F (1 + N √F)

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 610 Gate Delay Ratio of Intrinsic Delay Fanout factor, F Unsized Optimum delay Two-stage delay Optimum N N-stage delay J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, pp

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 611 Sizing for Energy Minimization Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing. Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, pp

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 612 Sizing for Energy Minimization Cg1Cg1 CLCL t p = t p0 [(1+f) + (1+F/f )] = t p0 (2+ f + F/f ) F= C L /C g1 t p0 ~V DD /(V DD - V th ) Energy consumption, E=V DD 2 C g1 [1+(1+f)+(f+F)] =V DD 2 C g1 [2+2f+F] f 1

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 613 Holding Delay Constant Reference circuit: f = 1, supply voltage = V ref Reference circuit: f = 1, supply voltage = V ref Size the circuit such that the delay of the new circuit is smaller than or equal to the reference circuit: Size the circuit such that the delay of the new circuit is smaller than or equal to the reference circuit: t p t p0 (2+f+F/f ) V DD V ref -V th 2+f+F/f t p t p0 (2+f+F/f ) V DD V ref -V th 2+f+F/f ── = ──────── = ── ──── ───── ≤ 1 t pref t p0ref (3+F ) V ref V DD -V th 3+F

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 614 Supply Voltage Vs. Sizing f V DD (volts) F = f opt ≈ √F V ref = 2.5V V th = 0.5V

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 615 Energy E V DD f + F ── = ─── ────── E ref V ref F

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 616 Normalized Energy Vs. Sizing f Normalized Energy F = f opt ≈ √F V ref = 2.5V V t = 0.5V

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 617 Summary Device sizing combined with supply voltage reduction reduces energy consumption. Device sizing combined with supply voltage reduction reduces energy consumption. For large fan-out energy reduction by a factor of 10 is possible. For large fan-out energy reduction by a factor of 10 is possible. An exception is F = 1 case, where the minimum size device is also the most effective one. An exception is F = 1 case, where the minimum size device is also the most effective one. Oversizing the devices increases energy consumption. Oversizing the devices increases energy consumption.