Division Discussion D11.3

Division

Division 8-bit/4-bit = 4: _ numer[8:0] denom[3:0] If denom < numer[7:4] then overflow (quotient won’t fit in 4 bits) Let T = numer[8:4] N = numer[3:0] N2 = denom[3:0]

Division 8-bit/4-bit = 4: shl TN N2 for I in 0 to 3 loop shl T & N; if T[4:0] >= N2 then T := T - (0 & N2); N(0) := ‘1’; end if; end loop;

Division 8-bit/4-bit = 4: sll TN N sub1sll sll sub1sll rem quot

-- Title: Division: 8/4 = 4:4 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity div is port ( numer: in STD_LOGIC_VECTOR (7 downto 0); denom: in STD_LOGIC_VECTOR (3 downto 0); quot: out STD_LOGIC_VECTOR (3 downto 0); remain: out STD_LOGIC_VECTOR (3 downto 0) ); end div; div.vhd Combinational divide

architecture div_arch of div is begin div1: process(numer, denom) variable T, N2: STD_LOGIC_VECTOR (4 downto 0); variable N: STD_LOGIC_VECTOR (3 downto 0); TN N2 begin T := '0' & numer(7 downto 4); N := numer(3 downto 0); N2 := '0' & denom; div.vhd (cont.)

for I in 0 to 3 loop T := T(3 downto 0) & N(3); N := N(2 downto 0) & '0'; if T >= N2 then T := T - N2; N(0) := '1'; end if; end loop; quot <= N; remain <= T(3 downto 0); end process div1; end div_arch; shl TN N2 div.vhd (cont.)

div synthesized circuit numer(2:0) denom(3:0) remain(3:0) quot(3:0) numer(7:3)

Top-level Design

-- Title: DIV Test library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; entity DIVtest is port( mclk : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(7 downto 0); BTN : in STD_LOGIC_VECTOR(3 downto 0); LD : out STD_LOGIC_VECTOR(7 downto 0); AtoG : out STD_LOGIC_VECTOR(6 downto 0); AN : out STD_LOGIC_VECTOR(3 downto 0) ); end DIVtest; DIVtest.vhd

architecture DIVtest_arch of DIVtest is signal r, p: std_logic_vector(15 downto 0); signal clr, clk, cclk: std_logic; signal clkdiv: std_logic_vector(23 downto 0); signal denom: std_logic_vector(3 downto 0); constant bus_width: positive := 4; begin clr <= BTN(3); -- Divide the master clock (50Mhz) process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; cclk <= clkdiv(17); Hz

p(15 downto 8) <= " "; denom <= '0' & BTN(2 downto 0); U1: divg generic map(width => bus_width) port map (numer => SW, denom => denom, quot => p(3 downto 0), remain =>p(7 downto 4)); U3: x7segb port map (x => p, cclk => cclk, clr => clr, AtoG => AtoG, AN => AN); LD <= SW; end DIVtest_arch;

x7segb AtoG(6:0) AN(3:0) x(15:0)

-- Title: Division: 2*width/width = width:width library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity divg is generic(width:positive); port ( numer: in STD_LOGIC_VECTOR (width+width-1 downto 0); denom: in STD_LOGIC_VECTOR (width-1 downto 0); quot: out STD_LOGIC_VECTOR (width-1 downto 0); remain: out STD_LOGIC_VECTOR (width-1 downto 0) ); end divg; divg.vhd

architecture divg_arch of divg is begin div1: process(numer, denom) variable T, N2: STD_LOGIC_VECTOR (width downto 0); variable N: STD_LOGIC_VECTOR (width-1 downto 0); begin T := '0' & numer(width+width-1 downto width); N2 := '0' & denom; N := numer(width-1 downto 0); divg.vhd (cont.)

begin T := '0' & numer(width+width-1 downto width); N2 := '0' & denom; N := numer(width-1 downto 0); for j in 0 to width-1 loop T := T(width-1 downto 0) & N(width-1); N := N(width-2 downto 0) & '0'; if T >= N2 then T := T - N2; N(0) := '1'; end if; end loop; quot <= N; remain <= T(width-1 downto 0); end process div1; end divg_arch;

width = 8