What Happened Yesterday Steve Holt *ADC speed does not necessarily depend on clock speed; GHz crystal not needed Mihir Ravel *Voltage tolerance of the peak- and-hold is V; use gain and offset *What’s the bandwidth of our peak- and-hold? We’ll measure this (worrying only about the high frequency end), but it’s likely less than 100 ns *When do we pull the value from the peak-and-hold? Make this software-controlled, taking a fixed amount of time

Signal Shape Quick rise time w/ slow decay time Impulse response of peak-and-hold circuit is first-order; exponential decay …Implement a fixed delay from peak to ADC sampling? 1 μs 2 μs

All X-ray pulses have this characteristic fast-rise, slow-decay shape. That means a higher pulse, despite having a longer wait-period to ADC conversion, will still be detected as a higher voltage.

New Method 1) Comparator detects threshold crossing; start waiting using trigger-event on comparator’s rising edge 2) Wait for a fixed, user-controlled amount of time using firmware counter; enable A/D 3) Data read after maximum A/D time (or query and loop) 4) Reset the comparator When to sample from the peak-and-hold? Old Method Sample once the signal goes below threshold Find this point using comparator/latch

*System architecture layout w/ interfaces *Detailed timing diagram w/ labels and estimated times Additional Tasks Begin documentation. Discuss the signals that the MCA is going to be detecting. Note their Poisson distribution. Describe the signals as impulses w/ fast rise-time and slow decay. Also, talk about the portability of the MCA for a variety of detectors. Note the rise-time is dependent on detector type. Look up peripheral devices that support high- speed USB such as RISC or CPLDs