1 CALICE simulation results G.Villani oct. 06 Progress on CALICE MAPS detector simulations: Results for 1.8 x 1.8 µm 2 Discussions & conclusions Next step

2 Cell size: 50 x 50  m x 1.8 μm 2 diode size 21 hits simulated, 5  m pitch 121 extrapolated hits / pixel 961 extrapolated hits / cell Pixel layout Cell  m 3.5x3.5  m x1.8  m 2 Simulated cell ( 3 x 3 pixels) layout CALICE simulation results G.Villani oct. 06

3 Σ diodes Collected charge vs (x,y) 0V 1.5 V 3.3 V Bias Diode : 1.5V fixed Nwell: 3.3V Pwell: 0V Subs: floating Epitaxial thickness: 12  m Noticeable improvement compared to the 0.9 x 0.9 µm 2 diodes

4 Central cell Q coll (x,y) sample 0.9 μm Comparator’s threshold: 50 e - Comparator’s threshold: 75 e - Comparator’s threshold: 100 e - Comparator’s threshold: 125 e - Comparator’s threshold: 150 e - Comparator’s threshold: 175 e - Comparator’s threshold: 200 e - Pixel coverage (e - threshold)  e - Comparator’s threshold: 225 e - Comparator’s threshold: 250 e - e-e- Diode 1.8 x 1.8 μm 2 e-e- Diode 0.9 x 0.9 μm 2 S cnt S sq CALICE simulation results G.Villani oct. 06 Central cell Q coll (x,y) sample 1.8 μm

5 CALICE simulation results G.Villani oct. 06 ≈38 ns≈25 ns ≈3 ns ≈300 ns 0.1* Charge collected by diodes and central Nwell Diode 1.8 x 1.8 μm 2 Diode 0.9 x 0.9 μm 2 ~ 120 ~ 175 diodes NWell e-e- e-e-

6 Charge collection time (x,y) CALICE simulation results G.Villani oct ns300 ns250 ns Diode 1.8 x 1.8 μm 2 Diode 0.9 x 0.9 μm 2 Pixel area of completed charge collection

7 CALICE simulation results G.Villani oct e - 75 e e e e e e e e -  Charge collected in t = 100 ns following a hit  Charge collected for t > 100 ns for the next 500 ns t =0) T ≥ 100ns T = 100ns Threshold setting ≥ 125 e - guarantees no double hit (i.e. not enough charge collected in the next time slot to set the comparator) After 100ns the diode current integration starts again

8 Increased diodes size to 1.8 x 1.8  m 2 significantly improves performance Minimum Σ charge signal ~ 200 e - for full transient Collection time ~ 250 ns for pixel coverage Collected charge in t = 100 ns for threshold 150 e - guarantees good pixel coverage ( estimation of % of area loss in progress) and no double hit S/N achievable with current configuration versus % of area loss in progress ( ‘mapping’ see figure) Conclusions CALICE simulation results G.Villani oct. 06 Next step: S/N ~ 10 for good pixel coverage within 100ns seems to be achievable  Further improvement in diode layout (i.e. more diodes) in progress: S/N ~ 10 for good pixel coverage within 100ns seems to be achievable (i.e. no need for P + implant, alternative layout et cetera) process information  To improve reliability of simulations (see above) it is strongly advisable to obtain process information Power consumption  Power consumption issue needs addressing S/N [100ns,min(% area)] D[nr] D[sz]