Hardware accelerator for PPC microprocessor By: Instructor: Kopitman Reem Fiksman Evgeny Stolberg Dmitri

Abstract Problem There are complex functions (e.g. FFT) which takes a lot of CPU recourses Consider the ways of implementation of such functions and choose the best solution according to specified constraints Solutions Pure SW implementation Pure HW implementation Combinational HW + SW - ASC technology

ASC - A Stream Compiler Combinational (SW/HW) code Familiar C++ writing Generates a flexible HW Standard NetList output (edif) Supported by standard Cad tools Provides HW optimization UNIX oriented

Design Approach - general FPGA module PPC405 Processor Memory EDAC Memory EDAC Memory DRAM Peripheral ASC Peripheral module Monitor other peripheral Monitor module System Bus (PLB)

ASC interface (General view) DMA engine DMA Buffer Sync. registers Generic Module PLB bus Interrupt controller FIFO_in FIFO_out Data Addr CTRL Fifo_full Data_in Data_out

SW review – main algorithm Start/reset System blocks initialization(FIFO, DMA,GPIO,LCD) DMA busy Yes Write data packets to ASC application No Calculatio n complete No Read data packets from ASC application Yes

iDCT running results – SW vs. HW