CSCE 212 Quiz 9a – 4/1/11 For the following questions, assume the clock cycle times given above and the following set of instructions: lw $5, -16($5) sw.

Slides:

Advertisements

Similar presentations

Pipeline Exceptions & ControlCSCE430/830 Pipelining in MIPS MIPS architecture was designed to be pipelined –Simple instruction format (makes IF, ID easy)

Advertisements

COMP381 by M. Hamdi 1 (Recap) Pipeline Hazards. COMP381 by M. Hamdi 2 I n s t r. O r d e r add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11.

CMSC 611: Advanced Computer Architecture Pipelining Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material adapted.

Advanced Computer Architectures Laboratory on DLX Pipelining Vittorio Zaccaria.

COMP25212 Further Pipeline Issues. Cray 1 COMP25212 Designed in 1976 Cost $8,800,000 8MB Main Memory Max performance 160 MFLOPS Weight 5.5 Tons Power.

1 Questions For the following code sequence ADD R1, R2, R3 SHL R3, R4, R5 SUB R1, R6, R3 SUB R5, R3, R1 (a)How many potential data hazards are there? (b)

Lecture Objectives: 1)Define pipelining 2)Calculate the speedup achieved by pipelining for a given number of instructions. 3)Define how pipelining improves.

CMPT 334 Computer Organization

Datorteknik DelayedLoad bild 1 Delayed Load. Datorteknik DelayedLoad bild 2 All problems solved? NO, what will happen if lw $6 $0($1) add $4 $6.

Instructor: Senior Lecturer SOE Dan Garcia CS 61C: Great Ideas in Computer Architecture Pipelining Hazards 1.

S. Barua – CPSC 440 CHAPTER 6 ENHANCING PERFORMANCE WITH PIPELINING This chapter presents pipelining.

1 Lecture 17: Basic Pipelining Today’s topics:  5-stage pipeline  Hazards and instruction scheduling Mid-term exam stats:  Highest: 90, Mean: 58.

1 Lecture 4: Advanced Pipelines Data hazards, control hazards, multi-cycle in-order pipelines (Appendix A.4-A.10)

CSCE 212 Quiz 4 – 2/16/11 *Assume computes take 1 clock cycle, loads and stores take 10 cycles and branches take 4 cycles and that they are running on.

1 Recap (Pipelining). 2 What is Pipelining? A way of speeding up execution of tasks Key idea : overlap execution of multiple taks.

Pipelining Andreas Klappenecker CPSC321 Computer Architecture.

CSCE 212 Quiz 9 – 3/30/11 1.What is the clock cycle time based on for single-cycle and for pipelining? 2.What two actions can be done to resolve data hazards?

1 Lecture 4: Advanced Pipelines Control hazards, multi-cycle in-order pipelines, static ILP (Appendix A.4-A.10, Sections )

Computer Architecture - A Pipelined Datapath A Pipelined Datapath  Resisters are used to save data between stages. 1/14.

CSCI 6307 Foundation of Systems – Exercise (2) Xiang Lian The University of Texas – Pan American Edinburg, TX

Pipelining Enhancing Performance. Datapath as Designed in Ch. 5 Consider execution of: lw $t1,100($t0) lw $t2,200($t0) lw $t3,300($t0) Datapath segments.

Morgan Kaufmann Publishers

Comp Sci pipelining 1 Ch. 13 Pipelining. Comp Sci pipelining 2 Pipelining.

Chapter 4 The Processor. Chapter 4 — The Processor — 2 Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined.

Pipeline Hazards. CS5513 Fall Pipeline Hazards Situations that prevent the next instructions in the instruction stream from executing during its.

Pipeline Data Hazards Warning, warning, warning! Read 4.8 Peer Instruction Lecture Materials for Computer Architecture by Dr. Leo Porter is licensed under.

1  1998 Morgan Kaufmann Publishers Chapter Six. 2  1998 Morgan Kaufmann Publishers Pipelining Improve perfomance by increasing instruction throughput.

Instructor: Senior Lecturer SOE Dan Garcia CS 61C: Great Ideas in Computer Architecture Pipelining Hazards 1.

Introduction to Computer Organization Pipelining.

MIPS processor continued. Performance Assume that – Memory access: 200ps – ALU and adders: 100 ps – Register file read: 50ps – Register file write: 10ps.

CSCE 212 Chapter 6 Enhancing Performance with Pipelining Instructor: Jason D. Bakos.

1 Pipelining CDA 3101 Discussion Section Question 1 – 6.1 Suppose that time for an ALU operation can be shortened by 25% in the following figure.

MIPS processor continued. Review Different parts in the processor should be connected appropriately to be able to carry out the functions. Connections.

Exercise 4.2 The basic single-cycle MIPS implementation in Figure 4.2 can only implement some instructions. New instructions can be added to an existing.

EECS 370 Discussion smbc-comics.com.

CS2100 Computer Organization

Pipelining Chapter 6.

CSCI206 - Computer Organization & Programming

Basic Pipeline Datapath

ECS 154B Computer Architecture II Spring 2009

CDA 3101 Spring 2016 Introduction to Computer Organization

Data Hazards and Stalls

Data Hazards and Stalls

SOLUTIONS CHAPTER 4.

Pipelining review.

Pipelining Chapter 6.

Current Design.

Lecture 18: Pipelining Today’s topics:

CSCI206 - Computer Organization & Programming

CSCI206 - Computer Organization & Programming

Data Hazards Data Hazard

Pipelining Chapter 6.

Single Cycle vs. Multiple Cycle

Lecture 18: Pipelining Today’s topics:

Daxia Ge Friday February 9th, 2007

Pipelining: Basic Concepts

Lecture 4: Advanced Pipelines

Delayed Load What will happen if lw $6 $0($1) add $4 $6 $1

Pipelining Chapter 6.

Appendix C Practice Problem Set 1

Morgan Kaufmann Publishers The Processor

Pipelining Chapter 6.

Guest Lecturer: Justin Hsia

Problem ??: (?? marks) Consider executing the following code on the MIPS pipelined datapath: add $t5, $t6, $t8 add $t9, $t5, $t4 lw $t3, 100($t9) sub $t2,

Need to stall for one cycle.

Presentation transcript:

CSCE 212 Quiz 9a – 4/1/11 For the following questions, assume the clock cycle times given above and the following set of instructions: lw $5, -16($5) sw $5, -16($5) add $5, $5, $5 1.What is the total execution time of this instruction sequence without forwarding and with full forwarding? 2.What is the speed-up achieved by adding full forwarding to a pipeline that had no forwarding? * ALU instruction can forward a value to EX stage of next instruction. Without forwardingWith full forwarding* 200 ps250 ps

CSCE 212 Quiz 9a Answers First determine nops and total clock cycles. WithoutWithlw $5, -16($5)nop nopsw $5, -16($5) sw $5, -16($5)add $5, $5, $5 add $5, $5, $5 (7 + 2 clock cycles)(7 + 1 clock cycles)

CSCE 212 Quiz 9a Answers 1.What is the total execution time of this instruction sequence without forwarding and with full forwarding? Without(7 + 2) x 200ps = 1800ps With(7 + 1) x 250ps = 2000ps

CSCE 212 Quiz 9a Answers 2.What is the speed-up achieved by adding full forwarding to a pipeline that had no forwarding? 1800/2000 = 0.90 (actually a slowdown)