Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #9: Smart Cart 525 Stage IX: 16 Mar Chip Level Layout

Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count Schematic Design Component Layout Functional Block Layout DRC of functional blocks LVS of functional blocks Chip Level Layout (98.56% Done) 3 Main blocks (each block LVSes) Full chip LVS  Simulations

Design Decisions Decided to route more wires over the SBOX and use metal 4 to reach registers on the right Move items in the encryption block higher up and redesign SBOX logic

Previously…

Currently ( x )

Updated Transistor Count OldNew Encryption13,05413,904 Multiplier Adder SRAM2276 Logic Registers (inputs/outputs)2540 Total20,85622,040

Updated Floorplan Area:Old (μm 2 )New (μm 2 ) Encryption68,35260,983 Multiplier Adder SRAM10, Logic/Wiring14,655 Registers (inputs/outputs, counters) Total110,96891,365 Density: ( transistors/μm 2 ) Aspect ratio:

Layer Masks Poly

Layer Masks Metal1

Layer Masks Metal2

Layer Masks Metal3

Layer Masks Metal4

Layout: Multiplier

Layout: SRAM/Adder

Layout: FinalText/Initial Permutation

Layout: Mix Column/Rcon

Layout: Key Expand

Layout: SBOX

Problems & Questions Registers problematic How can we make the chip smaller? Re-doing many of the blocks, learn from previous mistakes. Reset signal strength and buffer size needed for it. White space reduction Simulations take a long time.