Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing Puneet Gupta 1 Andrew B. Kahng 1,2,3 O.S. Nakagawa 1 Kambiz Samadi 2 (1) Blaze DFM, Inc., Sunnyvale, CA (2) ECE Department, University of California at San Diego (3) CSE Department, University of California at San Diego

Outline Introduction Lithographic Considerations for Interconnect Topography-Aware Optical Proximity Correction Post-Lithography Sign-off for Wires Manufacturing Non-Idealities and Interconnect Performance Impact of CMP Fill on Interconnect Capacitance Impact of Floating and Grounded Fill Intelligent Fill Synthesis Conclusions

Introduction Interactions among parasitic extraction, CMP fill, topography and lithography require explicit modeling Optical Proximity Correction (OPC) methods are oblivious to predictable nature of focus variation OPC methods cannot perfectly correct for lithographic and etch deviations CMP fill needed for uniformity of post-CMP wafer topography, but has significant impact on coupling and total capacitance This talk: example elements of “closed-loop” methodology for intelligent fill that unifies manufacturing-aware BEOL analyses and optimizations

Outline Introduction Lithographic Considerations for Interconnect Topography-Aware Optical Proximity Correction Post-Lithography Sign-off for Wires Manufacturing Non-Idealities and Interconnect Performance Impact of CMP Fill on Interconnect Capacitance Impact of Floating and Grounded Fill Intelligent Fill Synthesis Conclusions

Topography-Aware Optical Proximity Correction The depth-of-focus (DOF) variation corresponding to thickness variation severely affects the metal patterning of the subsequent upper layer Standard OPC (SOPC) assigns zero defocus for each layer which will lead to CD variation of the metal feature that will be placed on that layer Topography-aware OPC (TOPC) will compensate for thickness variation and will adjust the OPC and ORC (Optical Rule Check) accordingly

TOPC Motivation Post-CMP t1t1 (a) (b) Metal Layer t2t2 (a) Side view showing thickness variation over regions with dense and sparse layout. (b) Top view showing CD variation when a line is patterned over a region with uneven wafer topography, i.e., under conditions of varying defocus. Need modified OPC technique that is aware of post-CMP topography variation

TOPC Methodology CMP Simulation DOF Marking Layer Library & Technology GDSII Input GDSII for TOPC TOPCed GDSII DOF Model Database TOPC SOPC SOPCed GDSII Standard OPC Flow A map of thickness variation from Chemical-mechanical planarization (CMP) simulation is converted to DML (Defocus Marking Layer) and then fed into GDSII for TOPC TOPC applies different DOF models to metal lines according to DML

K-DML Assignment Problem Must assign each feature to DML partition according to its height used for OPC, and ORC calculations However, assigning two features within the distance of R to different DML partition will result in Optical Error Objective: Partition of all features into k DMLs to minimize the number of optical errors Distance < R

TOPC Results widthheightdelaywidthheightdelay%diffwidthheightdelay%diff Comparison of the timing delay using SOPC and TOPC; The units for width, height and delay are nm, nm, and ps, respectively. TOPCSOPC TestcaseReduction of EPE Count with +/- 6nm EPE range (%) Reduction of EPE Count with +/- 7nm EPE range (%) Benchmark Benchmark Comparison of edge placement error (EPE) count reductions with SOPC and TOPC.

Outline Introduction Lithographic Considerations for Interconnect Topography-Aware Optical Proximity Correction Post-Lithography Sign-off for Wires Manufacturing Non-Idealities and Interconnect Performance Impact of CMP Fill on Interconnect Capacitance Impact of Floating and Grounded Fill Intelligent Fill Synthesis Conclusions

Post Lithography Sign-off for Wires (PLSW) PLSW accounts for deviations between drawn and printed shapes As geometries keep on scaling, modeling process variations becomes important A methodology for estimating interconnect performance based on wafer shape contours of interconnect rather than drawn layout

PLSW for Analysis Litho Simulation Original SPEF Modified SPEF Reshape Engine Incremental RCX Original GDSII Modified GDSII PLSW RCX

PLSW Results Resistance Impact Capacitance Impact OPC Print Image 90nm technology M2 Wires (a)(b)

Outline Introduction Lithographic Considerations for Interconnect Topography-Aware Optical Proximity Correction Post-Lithography Sign-off for Wires Manufacturing Non-Idealities and Interconnect Capacitance Impact of CMP Fill on Interconnect Capacitance Impact of Floating and Grounded Fill Intelligent Fill Synthesis Conclusions

Interconnect Sidewall Angle Manufacturing non-idealities can occur along the sidewall of a wire due to etch To accurately account for interconnect parasitics these geometric changes needs to be modeled Sidewall angles can decrease the total capacitance by more than 10% Min-width =( min spacing) 0.20 um Metal thickness 0.35 um ILD thickness0.35 um C NT : Capacitance with non-zero sidewall angle C T : Capacitance with zero sidewall angle

Simple Equivalent-Width Methodology Non-vertical sidewalls imply a capacitance between non-parallel (sidewall) plates Capacitance between non-parallel plates can be calculated according to the following equation: ww IdealReal Comparison of ideal and real Interconnect cross-section. (1) d Cond_aCond_b h

Interconnect Sidewall Angle We use the average of the top and bottom width of the wire as its new equivalent width Simulation Configuration

Outline Introduction Lithographic Considerations for Interconnect Topography-Aware Optical Proximity Correction Post-Lithography Sign-off for Wires Manufacturing Non-Idealities and Interconnect Performance Impact of CMP Fill on Interconnect Capacitance Impact of Floating and Grounded Fill Intelligent Fill Synthesis Conclusions

Impact of CMP Fill on Interconnect Capacitance To enhance uniformity of post-CMP wafer topography, dummy fill is inserted In addition to improving feature density uniformity, dummy fill also changes coupling and total capacitance of functional interconnects Different fill/wire geometries have different impact on interconnect capacitance

Basic Simulation Configurations wmwm wfwf lflf d ko sxsx sysy AABBAB y x (1)(2)(3) A wmwm wfwf lflf d ko y x

Impact of Floating Fill on Interconnect Capacitance Change in coupling capacitance due to changes in fill width Change in total capacitance due to changes in fill width

Impact of Floating Fill on Interconnect Capacitance Change in coupling capacitance due to changes in fill length Change in total capacitance due to changes in fill length

Impact of Grounded Fill on Interconnect Capacitance Change in total capacitance due to changes in fill width Change in total capacitance due to changes in fill length

Impact of CMP Fill on Interconnect Capacitance Fill insertion can dramatically increase C c and C tot over their respective nominal values –G-M-G, 90nm, Intermediate: C c 24X, C tot 10% Useful fill pattern design guidelines may be possible, e.g.: –If the number of fill rows (M) is fixed, use as many fill columns (N) as possible –If the number of fill columns (N) is fixed, use as few fill rows (M) as possible Cf. VMIC-2004 invited paper (UCSD / UCLA) Additional studies needed with tighter pitches, more exhaustive analysis of fill patterns, etc.

Impact of Via Fill on Wire Capacitance CaseCapacitance (fF) Without Via Fill With Via Fill Change2.1% What is impact of via fill on total wire capacitance? Change in capacitance with and without via fill is insignificant Metals in M+1, M, and M+1 layers already create shielded wall  any additional metals, such as vias, do not have any significant additional impact on capacitance

Intelligent Fill Synthesis Traditional fill synthesis methods are reaching their limits of usefulness One indication: emergence of so-called “recommended rules” The impact of fill synthesis on timing continues to be a key for the designer A more sophisticated, dedicated CMP fill synthesis – “intelligent fill synthesis” - can potentially reduce engineering effort and enhance manufacturability

Intelligent Fill Synthesis We believe that intelligent fill synthesis must embody the following features: Multilayer Density Control Perform concurrent minimization of density variation of multiple layers as well as each individual layer Model-Based Fill Synthesis Identify the regions where planarity is important and attempt to minimize topography variation Timing-Driven Fill Synthesis Assess impact of inserting fills on timing Keep-out distances computed for each net to avoid wasteful “one size fits all” keep-out distance

Conclusions We have studied the impact of two manufacturing process variation sources – wafer topography and sidewall angle – on the design process We have also studied the impact of floating and grounded dummy fills on coupling and total interconnect capacitance Finally, we have described elements of “intelligent fill synthesis” and how it can be used in a timing-driven fill methodology Our ongoing research studies further aspects of the manufacturing flows for which intelligent fill is relevant

Thanks for your attention