Trend towards Embedded Multiprocessors Popular Examples –Network processors (Intel, Motorola, etc.) –Graphics (NVIDIA) –Gaming (IBM, Sony, and Toshiba) –Research (RAW, IWarp, etc.) May 11, 2005 Design Flow from Domain Specific Languages to Embedded Multiprocessors William Plishker Kaushik Ravindran Kurt Keutzer The processor is the basic building block Software flexibility is key For application specific programmable systems to succeed, it is necessary to deliver high- performance implementations quickly Programming Challenges –Multiple processing elements –Heterogeneous memories –Special purpose hardware Domain Specific Languages –DSLs are tailored to an application domain with: –component libraries –communication and computation semantics –visualization tools –test suites Implementation Gap Natural representation of Application FromDevice(0) Discard ToDevice(0) FromDevice(1) FromDevice(2) FromDevice(3) Discard ToDevice(1) ToDevice(2) ToDevice(3) Discard … FromDevice(15) Lookup IPRoute ToDevice(15) …… IPVerify DecIPTTL Discard IPVerify DecIPTTL Discard IPVerify DecIPTTL … Discard DecIPTTL Discard DecIPTTL Low Level Programming Environment Proposed Design Approach –Application specification in domain specific language (DSL) –Abstract model of architecture and transform application to execution model –Automated mapping from execution model to target architecture Application description High-level optimizations Execution Model Architecture configuration HW / SW partitioning Task allocation Communication assignment Compilation / Synthesis Profile PEFPGA PEFPGA PEFPGA PEFPGA MEM From (0)To (0) From (1)To (1) Lookup IPRoute Key Models Computation Model –Abstract model to represent concurrency –Natural to the application domain Architectural Model –Capture those features of the architecture which most impact performance –Define components which must be annotated in the application to facilitate good mappings Execution Model –Description of computation on a target hardware –Task graph with platform specific computation and memory annotations Generating an Application Execution Model –Unravel application tasks to expose concurrency –Partition application components into tasks –Annotate memory and communication requirements Extract parallelism from application without explicit designer intervention Platform Dependent S1S1 S2S2 R1R1 L11L11 L21L21 T1T1 R2R2 L12L12 L22L22 T2T2 Receiv e Lookup Stage 1 Lookup Stage 2 Transmit Branch 1 Branch 2 Packet header Memory read Core Reg File Core Reg File Core ALU Core ALU Extension Reg Files Extension Reg Files Extension ALU Extension ALU Timers, Interrupts Instruction Fetch Data Load/Store $ $ $ $ System Bus Instruction RAM/ROM Instruction RAM/ROM Data RAM/ROM Data RAM/ROM XLMI (peripherals) XLMI (peripherals) Network Processor Application execution model Periodicity Communication requirements, shared resources Execution Model Computation requirements (per implementation option) Mapping Platform Independent FPGA logic Execution Model Computation requirements, Architecture constraints Execution Model Fabric and data requirements Application description in DSL Queue requirements Schedulable element rates Sequential programs Mapping Programs + MHS Mapping RTL Task  PE, Data  Memory, Comm  Interconnect/Memory Arbitration scheme selection Element tuning Configure Architecture PEs, Memory, Interconnect HW/SW Partitioning Element Implementation Selection Floor planning Translation to IXP-CTranslation to CTranslation to RTL Assign Element Implementation Options High-level Optimizations Form Task Graph boundaries MEM MB Soft Multiprocessor Mapping Procedure –Transform application description in DSL to execution model –Explore design space of the assignment of computation and communication to architectural resources –Produce set of sequential code to be handed off to traditional compilation techniques Design Space Exploration Analytical Models for the Architecture –Profile information for task execution times –Assume performance and communication requirements can be evaluated statically Constraint Formulation and Optimization Methods –Partition tasks between processing elements –Assign application state to memory –Assign communication to hardware links –Find optimal configuration to maximize some performance metric Current Work Mapping network applications to multiple platforms –Application in Click DSL –Target multiprocessors: IXP 2xxx network processor, Xilinx Virtex 2VP50 soft multiprocessor –Integer-linear programming approaches for task allocation ME ME Cluster ScratchpadSRAMSDRAM Hash Unit Media Switch Fabric XScale Intel IXP2800 Tensilica MPSoC ME ME Cluster ScratchpadSRAMSDRAM Hash Unit Media Switch Fabric XScale Example Flow