©UCB CS 161Computer Architecture Chapter 5 Instructor: L.N. Bhuyan LECTURE 10

©UCB Compose Datapath: R-form + Load/Store Registers Read Register 1 Read data 1 ALUALU Read data 2 Read Register 2 Write Register Write Data Instr- uction Zero ALU control 4 RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite 1Mux01Mux0 MemTo- Reg 0=R-form 1=L/S MuxMux ALUSrc 0 = R-format 1 = Load/Store Add muxes

©UCB Compose Datapath: … + Imem + PC Registers Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU control 4 RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite MuxMux MemTo- Reg MuxMux ALUSrc Read Addr Instruc- tion Imem “4” PCPC addadd

©UCB Compose Datapath: … + Branch Registers Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALUcon RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite MuxMux MemTo- Reg MuxMux ALUSrc Read Addr Instruc- tion Imem “4” PCPC addadd addadd << 2 MuxMux PCSrc “Left Shift 2” module What about jump?

©UCB Recap: Single-Cycle Datapath Registers Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU con RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite MuxMux MemTo- Reg MuxMux ALUSrc Read Addr Instruc- tion Imem “4” PCPC addadd addadd << 2 MuxMux PCSrc 4 Supports all MIPS-lite instrns?

©UCB Datapath: Miscellaneous Details °Wrinkle: destination registers may differ across instruction formats: R-format: [rd] <- [rs] op [rt] add$t0,$s0,$s1, For this instn, bits is destination (t0), which should be connected to the write reg. I-format:[rt] <- mem[[rs] + imm16] lw$t0,24($s3), For this instn, bits should go to the write port. Bits 0-15 go to the ALU as address. Connection to the write port changes! °Solution? mux to the rescue!

©UCB Datapath (add RegDst Mux) Regs Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU- con RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite MuxMux MemTo- Reg MuxMux Read Addr Instruc- tion Imem 4 PCPC addadd addadd << 2 MuxMux PCSrc ALU- src MuxMux 25:21 20:16 15:11 RegDst 15:0 31:0

©UCB Datapath: Miscellaneous Details °What if instruction is a conditional branch ( beq )? if operands equal, take branch (PC gets PC+4+offset) else PC gets PC+4 °Therefore, set control point PCSrc = 1 if and only if beq and Zero asserted

©UCB Datapath (add Branch control point) Regs Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU- con RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite MuxMux MemTo- Reg MuxMux Read Addr Instruc- tion Imem 4 PCPC addadd addadd << 2 MuxMux ALU- src MuxMux 25:21 20:16 15:11 RegDst 15:0 31:0 Branch PCSrc

©UCB Adding Control °CPU = Datapath + Control °Single-Cycle Design: Instruction takes exactly one clock cycle Datapath units used only once per cycle Writable state updated at end of cycle °What must be “controlled”? Multiplexors (Muxes) Writable state elements: Register File, Data Memory (Dmem) -what about PC? Imem? ALU (which operation?)

©UCB Processor = Datapath + Control °Single-Cycle Design: everything happens in one clock cycle  until next falling edge of clock, processor just one big combinational circuit!!!  control is just a combinational circuit (output, just function of inputs) °outputs? control points in datapath °inputs? the current instruction! ( opcode, funct control everything)

©UCB Defining Control Control Logic op rs rt rd shamt funct R-format instruction To datapath 6 6

©UCB Defining Control °Note that funct field only present in R- format instruction - funct controls ALU only °To simplify control, define Main, ALU control separately – using multiple levels will also increase speed – important optimization technique °ALUop inputs will be defined Control Logic Main Control ALU control op funct op funct ALU- con ALUop

©UCB Defining ALU Control ALUcon ALUALU Zero Result ALUconALU functionInstruction(s) supported 0000ANDR-format (and) 0001ORR-format (or) 0010addR-format (add), lw, sw 0110subtractR-format (sub), beq 0111 set on less thanR-format (slt) 1100 NOR R-format (nor) ABAB

©UCB Defining ALU Control InstructionDesired opcodeALU ActionALUOpfunctALUcon lwadd 00xxxxxx 0010 swadd 00xxxxxx 0010 beqsubtract 01xxxxxx 0110 R-typeadd (add) 0010 R-typesubtract (sub) 0110 R-typelogical AND (and) 0000 R-typelogical OR (or) 0001 R-typeset on less (slt) 0111 ALUOp Funct Field a1a2f5f4f3f2f1f0ALUcon 00xxxxxx 0010 x1xxxxxx xxx xxx xxx xxx xxx Don’t Cares

©UCB Deriving ALUcon outputs From the truth table, output signals can be easily derived because of don’t cares. Operation2 (msb) = ALUOp0 OR (ALUOp1 AND F1) Operation1 = ALUOp1 NOR F2 Operation0 (lsb) = ALUOp1 AND (F3 OR F0) ALUOp is supplied by the main control unit (to be designed) and F0-F5 are the lsbs of the instruction.

©UCB Fully Minimized ALU Control Operation2 Operation1 Operation0 ALUOp1 F3 F2 F1 F0 ALUOp0 ALUOp ALUcon 4th bit=0 funct

©UCB Datapath + ALU Control Registers Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU- con RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite MuxMux MemTo- Reg MuxMux Read Addr Instruc- tion Imem “4” PCPC addadd addadd << 2 MuxMux PCSrc ALU Control Instr[5:0] ALUOp ALU- src

©UCB Implementing Main Control Main Control RegDst Branch MemRead MemtoReg ALUop MemWrite ALUSrc RegWrite op 2 Main Control has one 6-bit input, 9 outputs (7 are 1-bit, ALUOp is 2 bits) To build Main Control as sum-of-products: (1) Construct a minterm for each different instruction (or R-type); each minterm corresponds to a single instruction (or all of the R- type instructions), e.g., M R-format, M lw (2) Determine each main control output by forming the logical OR of relevant minterms (instructions), e.g., RegWrite: M R-format OR M lw

©UCB Single-Cycle MIPS-lite CPU Regs Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU- con RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite MuxMux MemTo- Reg MuxMux Read Addr Instruc- tion Imem 4 PCPC addadd addadd << 2 MuxMux ALU Control 5:0 ALUOp ALU- src MuxMux 25:21 20:16 15:11 RegDst 15:0 31:0 Branch Main Control op=[31:26] PCSrc

©UCB Adding Jal instrn to datapath 1.Jal consists of jump and link for function calls – jump to the function address (j target) already implemented in Fig Place PC+4 (return address) in $ra. So (a) extend the mux at reg input to include 31 ($ra) as another input and (b) expand the mux at write data input to have PC+4 as another input. DRAW on Fig