7/2/2015445_23 1 Pipelining ECE-445 Computer Organization Dr. Ron Hayne Electrical and Computer Engineering.

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Presentation transcript:

7/2/ _23 1 Pipelining ECE-445 Computer Organization Dr. Ron Hayne Electrical and Computer Engineering

7/2/ _232 Pipelining F1F1 E1E1 I1I1 F2F2 E2E2 I2I2 F3F3 E3E3 I3I3 Sequential Execution F1F1 E1E1 I1I1 F2F2 E2E2 I2I2 F3F3 E3E3 I3I3 Pipelined Execution

7/2/ _233 Hardware Organization Instruction Fetch Unit Execution Unit Interstage Buffer B1

7/2/ _234 Four State Pipeline  Fetch (F) Read the instruction from memory  Decode (D) Decode the instruction and fetch the source operand(s)  Execute (E) Perform the operation specified by the instruction  Write (W) Store the result in the destination location

7/2/ _235 Four Stage Pipeline

7/2/ _236 Hardware Organization

7/2/ _237 Data Hazard  Pipeline stalled  Source or destination operands not available at time expected in the pipeline  Execution operation taking more than one clock cycle

7/2/ _238 Data Hazard

7/2/ _239 Data Dependency

7/2/ _2310 Operand Forwarding

7/2/ _2311 Operand Forwarding

7/2/ _2312 Handling Data Hazards in SW  Compiler detect data dependencies and deal with them Insert NOPs Attempt to reorder instructions to perform useful tasks in NOP slots  Side effects Instruction changes contents of a register other than the named destination Autoincrement/autodecrement addressing modes Condition code flags Give rise to multiple dependencies Should be minimized

7/2/ _2313 Instruction Hazards  Pipeline stalled  Delay in the availability of an instruction Cache miss Branch instructions

7/2/ _2314 Instruction Hazard

7/2/ _2315 Instruction Queue and Prefetch

7/2/ _2316 Branch Penalty

7/2/ _2317 Branch Prediction  Attempt to predict whether or not a particular branch will be taken  Speculative execution Continue to execute until outcome of branch evaluated No processor registers or memory can be updated until branch outcome is confirmed

7/2/ _2318 Branch Prediction  Static Branch Prediction Some branch instructions predicted as taken and others as not taken End or program loop Beginning of program loop Hardware or compiler  Dynamic Branch Prediction Based on execution history

7/2/ _2319 Structural Hazard  Two instructions require use of a given hardware resource at the same time Access to memory Separate instruction and data caches Access to register file Multiple port register file  In general avoided by providing sufficient hardware resources on the processor chip

7/2/ _2320 Structural Hazard

7/2/ _2321 Summary  Pipelining does not result in individual instructions being executed faster  Throughput increases Rate at which instruction execution is completed  Important goal in designing processors is to identify all hazards that may cause the pipeline to stall Find ways to minimize their impact

7/2/ _2322 Questions?