13-1 EE 319K Introduction to Microcontrollers Lecture 13: Serial Communications Interface (SCI), Producer-Consumer problems, FIFO Queues, Lab9 Read Book Sections 8.1, 8.2, , , 12.4

13-2 Ramesh Yerraballi Serial Comm. Interface (SCI)  This protocol is also known as UART (Universal Asynchronous, Receiver Transmitter)  Originally used to connect i/o terminals to mainframes.  Neither fast nor reliable but simple SCI Device Driver  Public routines  SCI1_Init  SCI1_InChar  SCI1_OutChar  Private Objects  SCI1CR2  SCI1BD  SCI1SR1  SCI1DRL

13-3 Ramesh Yerraballi SCI Basics  Baud Rate: The total number of bits transmitted per second baud-rate = 1/bit-time  Mode Bit (M): Selects 8- bit(M=0) or 9-bit (M=1) data frames  Frame: The smallest complete unit of serial transmission.  Bandwidth: The amount actual information transmitted per second. A serial data frame with M=0 number of information bits/frame Total number of bits/frame x baud-rate Bandwidth =

13-4 Ramesh Yerraballi Transmitting in Asynchronous Mode The software writes to SCI1DRL, then  8 bits of data are moved to the shift register  start and stop bits are added  shifts in 10 bits of data one at a time on TxD line  shift one bit per bit time (=1/baudRate) Data and shift registers implement the serial transmission

13-5 Ramesh Yerraballi Receiving in Asynchronous Mode The receiver waits for the 1 to 0 edge signifying a start bit, then  shifts in 10 bits of data one at a time from RxD line  shift one bit per bit time (=1/baudRate)  start and stop bits are removed  checked for noise and framing errors  8 bits of data are loaded into the SCIDRL Data and shift registers implement the receive serial interface

13-6 Ramesh Yerraballi SCI Details  SCI1BD : Determines the baud rate: Say SCI1BD[12:0] => Integer BR SCI Baud-rate = MClock/(16xBR) Mclock on 9S12DP512 is 24 MHz (with PLL in Load mode); 8 MHz otherwise.  TE is the Transmitter Enable bit  RE is the Receiver Enable bit.

13-7 Ramesh Yerraballi … SCI Details  TDRE is the Transmit Data Register Empty flag.  set by the SCI hardware if transmit data register empty  if set, the software can write next output to SCIDRL  cleared by two-step software sequence ofirst reading SCISR1 with TDRE set othen SCIDRL write  RDRF is the Receive Data Register Full flag.  set by hardware if a received character is ready to be read  if set, the software can read next input from SCIDRL  cleared by two-step software sequence ofirst reading SCISR1 with RDRF set othen SCIDRL read

13-8 Ramesh Yerraballi … SCI Details  RIE is the Receive Interrupt Enable bit (Arm).  set and cleared by software  set to arm RDRF triggered interrupts  clear to disarm RDRF triggered interrupts  TIE is the Transmit Interrupt Enable bit (Arm).  set and cleared by software  set to arm TDRE triggered interrupts  clear to disarm TDRE triggered interrupts  SCI1DRL register contains transmit and receive data  these two registers exist at the same I/O port address  Reads access the read-only receive data register (RDR)  Writes access the write-only transmit data register (TDR)

13-9 Ramesh Yerraballi SCI I/O Programming ; Initalize 9S12DP512 SCI at bps ; Inputs: none ; Outputs: none ; Errors: none ; assumes 8 MHz E clock (PLL not activated) SCI1_Init movb #$0c,SCI1CR2 ; enable SCI TE=RE=1 movw #13,SCI1BD ; bps ; baud rate(bps)= /(16xBR) ( ) rts

13-10 Ramesh Yerraballi …SCI I/O Programming

13-11 Ramesh Yerraballi …SCI I/O Programming Re-visit Tut3

13-12 Ramesh Yerraballi Overrun Error If there is already data in the SCI0DRL when the shift register is finished, it will wait until the previous frame is read by the software, before it is transferred. An overrun occurs when there is one receive frame in the SCI0DRL, one receive frame in the receive shift register, and a third frame comes into RxD.

13-13 Ramesh Yerraballi Tut2  Busy-wait SCI input  I/O bound (bandwidth limited to input rate)  Very inefficient (spends a lot of time waiting)

13-14 Ramesh Yerraballi Tut2: Recover wasted time? Technique 1: Combine all busy-waits  Requires cooperation,  Complicated to test (all tasks are interrelated)  Can’t guarantee bound on latency

13-15 Ramesh Yerraballi Tut2: Recover wasted time? Technique 2: Input device interrupts when ready  ISR reads new input, puts into FIFO  Latency equals maximum time it runs with I=1 FIFO queues and double buffers can be used to pass data from a producer to a consumer

13-16 Ramesh Yerraballi FIFO Queues Figure 12.6: FIFO queues can be used to pass data between threads

13-17 Ramesh Yerraballi Tut4: Producer Consumer problem

13-18 Ramesh Yerraballi FIFO: Two Implementations  Differ in the way empty/full conditions are determined:  Two pointers (12.3.3, Tut4): oEmpty => GetPt == PutPt oFull => GetPt ==(PutPt+1)%buffer_size oWastes 1 buffer slot  Two pointers with a counter oEmpty => counter == 0 oFull => counter = buffsize oUses all buffer slots

13-19 Ramesh Yerraballi FIFO: Two Implementations  Common to both Implementations  GetPt: Points to the data that will be removed on the next call to FiFo_Get  PutPt: Points to the empty space where the data will be stored on the next call to Fifo_Put  Fifo_Put adds data at PutPt and increments PutPt  FiFo_Get removes data at GetPt and decrements GetPt  Wrapping must be handled because buffers are not infinite

13-20 Ramesh Yerraballi Wrap Pointer wrap on 2nd put Pointer wrap on 4th get

13-21 Ramesh Yerraballi Lab9 Figure 8.3: Data flows from the sensor through the two microcontrollers to the LCD. The output compare timer is used to trigger the real-time sampling. Use the special serial cable to connect the two SCI1 ports. 1.5 cm 1.50 cm

13-22 Ramesh Yerraballi Lab9 Communication interfacing between two 9S12 microcontrollers using SCI

13-23 Ramesh Yerraballi Simple Design Courtesy: Jon Valvano

13-24 Ramesh Yerraballi Issues in Lab 9  Synchronization oBlind-Cycle oBusy Wait oInterrupt  FIFO  Structured mechanism to pass data.  Helps us cope with mismatched speeds of producer and consumer

13-25 Ramesh Yerraballi Lab 9 Transmitter  Context Switch  When a previously scheduled interrupt (OC interrupt) occurs, the processor has to switch context to run the corresponding ISR.  What does this entail: oThe current instruction (of the foreground process) is finished oPush registers (including CCR) on Stack (with I=0) oDisable further interrupts (I=1) oVector fetch and load ISR address into PC  Demo in TExaS with Transmitter

13-26 Ramesh Yerraballi …Lab 9 Transmitter  When does the OC Interrupt occur?  3 conditions must be true oArm the Specific Interrupt: (C0I=1) - ritual oInterrupts enabled: (I=0 using cli) - ritual oInterrupt gets Triggered: C0F is set when TCNT equals TC0  What happens in ISR?  Acknowledge Interrupt: movb #$01,TFLG1  Read ADC data, encode, send one frame  rti Note: It is not necessary for you to set/clear the I bit except in the initial ritual, it is done automatically

13-27 Ramesh Yerraballi Lab 9 Receiver  Context Switch  When a scheduled interrupt (SCI RDRF interrupt) occurs, the processor has to switch context to run the corresponding ISR.  When does the SCI RDRF Interrupt occur?  3 conditions must be true oArm the Specific Interrupt: (RIE=1) - ritual oInterrupts enabled: (I=0 using cli) - ritual oInterrupt gets Triggered: RDRF is set when a new frame arrives  What happens in ISR?  Acknowledge Interrupt: By reading SCI0SR1 and SCI0DRL  Read a frame and pass to foreground through global memory; Schedule  rti

13-28 Ramesh Yerraballi Lab 9: Why FIFO?  May use unstructured globals to pass data  Is there data in there?  Are you writing new data overtop old data?  Are you reading garbage?  FIFOs are structured globals  Fifo_Put stores data; Fifo_Get retreives data  First in first out means the data remains in order  Real way to implement thread synchronization oThe producer needs to stall if FIFO is full oThe consumer needs to stall if FIFO is empty  Lab7 way to implement thread synchronization oThe producer throws data away if FIFO is full oThe consumer waits if FIFO is empty

13-29 Ramesh Yerraballi Lab9: Receiver Main program 1.Initialize Timer, LCD, Fifo_Init, SCI 2.Fifo_Get (wait here until data is available) 3.Convert from 8-bit sample to decimal fixed-point 4.Display on LCD 5.repeat 2,3,4 over and over

13-30 Ramesh Yerraballi Interrupt Programming