Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 5, 2014 Dynamic Logic Midterm 2 Avg: 58 Std Dev.: 15

Today Clocking Dynamic (Clocked) Logic –Strategy –Form –Compare CMOS Penn ESE370 Fall DeHon 2

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Clocking Penn ESE370 Fall DeHon 4

Two Phase Non-Overlapping Clocks Build master-slave register from pair of latches Control with non-overlapping clocks Penn ESE370 Fall DeHon 5

Clocking Highlights Clock discipline simplifies logic composition –Abstracts many internal timing details –Just concerned with making clock period long enough Breaking logic up with registers allows to run at high frequency – reuse logic Discipline – keeping data stable around clock edge –Setup, hold time – determined by circuit –Clk  Q delay for data come out of register Penn ESE370 Fall DeHon 6

Clocking Circuits typically operate in a clocked environment Gives some additional structure we can exploit Penn ESE370 Fall DeHon 7

Dynamic Logic Penn ESE370 Fall DeHon 8

Motivation Like to avoid driving pullup/pulldown networks –reduce capacitive load Power, delay Penn ESE370 Fall DeHon 9

Motivation Like to avoid driving pullup/pulldown networks –reduce capacitive load Power, delay Ratioed had problems with –Large device for ratioing –Slow pullup –Static power Penn ESE370 Fall DeHon 10

Idea Use clock to disable pullup during evaluation Penn ESE370 Fall DeHon 11

Discuss Use clock to disable pullup during evaluation What happens when –/Pre=0, A=B=0 –/pre=1, A=B=0? –/pre=1, A=1, B=0? Sizing implication? Concerns? Requirements? Penn ESE370 Fall DeHon 12

Advantages Large device –Driven by clock, not data/logic –Can pullup quickly w/out putting load on logic Single network –Pulldown –Don’t have to size for ratio with pullup –Swings rail-to-rail Penn ESE370 Fall DeHon 13

Domino Logic Penn ESE370 Fall DeHon 14

Domino AND-OR Penn ESE370 Fall DeHon 15

Domino Everything charged high –After inverter all inputs low Why do we want this? Disabled, waiting for an enabling transition Penn ESE370 Fall DeHon 16

Requirements Single transition –Once fires, it is done  like domino falling All inputs at 0 during precharge –Precharge to 1 so inversion makes 0 Non-inverting gates Penn ESE370 Fall DeHon 17

Domino or4 Penn ESE370 Fall DeHon 18

Domino Logic Performance –R 0 /2 input Compare to CMOS cases? nor4 or4 nand4 Penn ESE370 Fall DeHon 19

Dynamic OR4 Precharge time? Driving input –With R 0 /2 Driving inverter and self cap? Output self delay? Penn ESE370 Fall DeHon 20

CMOS NOR4 Driving input –With R 0 /2 Driving self cap? Penn ESE370 Fall DeHon 21

CMOS NAND4 Driving input –w/ R 0 /2 Driving self cap? Penn ESE370 Fall DeHon 22

Issues Noise sensitive Power? Activity? Penn ESE370 Fall DeHon 23

Discuss (time permit) Avoid inversion? Converting from CMOS? Post-charge Penn ESE370 Fall DeHon 24

Observe Better (lower) ratio of input capacitance to drive strength Particularly good for –Driving large loads –Large fanin gates Harder to design with –Timing and polarity restrictions –Avoiding noise Especially with today’s high variation tech. Can consume more energy/op Penn ESE370 Fall DeHon 25

Idea Dynamic/clocked logic –Only build/drive one network –Fast transition propagation –Spend delay (capacitance) on pullup off critical path of logic –More complicated, power Reserve for when most needed Penn ESE370 Fall DeHon 26

Admin Homework 7 out –…and due on Tuesday Withdraw date Friday Penn ESE370 Fall DeHon 27