Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 6 CPU Design

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline CPU SpecificationCPU Specification Very Simple CPUVery Simple CPU Relatively Simple CPURelatively Simple CPU Simple CPU ShortcomingsSimple CPU Shortcomings 8085 Microprocessor8085 Microprocessor

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Specifying a CPU Determine its intended applicationsDetermine its intended applications Develop Instruction Set ArchitectureDevelop Instruction Set Architecture Design State DiagramDesign State Diagram

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU State Diagram

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Cycle FetchFetch DecodeDecode ExecuteExecute

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Very Simple CPU 64 x 8 memory64 x 8 memory –Address pins A[5..0] –Data Pins D[7..0] 8-bit Accumulator8-bit Accumulator

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Non-ISA Registers 6-bit Address Register AR6-bit Address Register AR 6-bit Program Counter PC6-bit Program Counter PC 8-bit Data Register DR8-bit Data Register DR 2-bit Instruction Register IR2-bit Instruction Register IR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetching Instructions from Memory CPU outputs address on A[5..0]CPU outputs address on A[5..0] Delay for memory to perform its internal operationsDelay for memory to perform its internal operations Read data from memory on D[7..0]Read data from memory on D[7..0]

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch States FETCH1: AR  PC

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch States FETCH1: AR  PC FETCH2: DR  M

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch States FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch States FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1 FETCH3: IR  DR[7..6], AR  DR[5..0]

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch State Diagram

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Decoding Instructions

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Executing Instructions - ADD ADD1: DR  M ADD2: AC  AC + DR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Executing Instructions - AND AND1: DR  M AND2: AC  AC ^ DR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Executing Instructions - JMP JMP1: PC  DR[5..0]

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Executing Instructions - INC INC1: AC  AC + 1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Very Simple CPU Specification FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1 FETCH3: IR  DR[7..6], AR  DR[5..0] ADD1: DR  M ADD2: AC  AC + DR AND1: DR  M AND2: AC  AC ^ DR JMP1: PC  DR[5..0] INC1: AC  AC + 1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Very Simple CPU State Diagram

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Establishing Data Paths Regroup operations by destination AR: AR  PC; AR  DR[5..0] PC: PC  PC + 1; PC  DR[5..0] DR: DR  M IR: IR  DR[7..6] AC: AC  AC + DR; AC  AC^DR; AC  AC + 1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Establishing Data Paths Determine functions of each component AR, DR, and IR only load dataAR, DR, and IR only load data PC and AC load and increment dataPC and AC load and increment data

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Preliminary Register Section

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR only supplies data to memoryAR only supplies data to memory

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR only supplies data to memoryAR only supplies data to memory IR only supplies data to control unitIR only supplies data to control unit

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR only supplies data to memoryAR only supplies data to memory IR only supplies data to control unitIR only supplies data to control unit AC does not supply data to other registersAC does not supply data to other registers

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR only supplies data to memoryAR only supplies data to memory IR only supplies data to control unitIR only supplies data to control unit AC does not supply data to other registersAC does not supply data to other registers Bus is 8-bits wide, but some registers have fewer bitsBus is 8-bits wide, but some registers have fewer bits

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR only supplies data to memoryAR only supplies data to memory IR only supplies data to control unitIR only supplies data to control unit AC does not supply data to other registersAC does not supply data to other registers Bus is 8-bits wide, but some registers have fewer bitsBus is 8-bits wide, but some registers have fewer bits ALU needed to generate resultsALU needed to generate results

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Final Register Section

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Very Simple ALU

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generic Hardwired Control Unit

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Design Heuristics Assign FETCH1 to counter value 0Assign FETCH1 to counter value 0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Design Heuristics Assign FETCH1 to counter value 0Assign FETCH1 to counter value 0 Assign sequential states to sequential valuesAssign sequential states to sequential values

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Design Heuristics Assign FETCH1 to counter value 0Assign FETCH1 to counter value 0 Assign sequential states to sequential valuesAssign sequential states to sequential values Optimize assignment of values to first states of execute routinesOptimize assignment of values to first states of execute routines

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 State Assignments Instruction First State IR ADDADD100 ANDAND101 JMPJMP110 INCINC111

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction First State IR Counter Value ADDADD (8) ANDAND (10) JMPJMP (12) INCINC (14) State Assignments

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Very Simple CPU Control Unit

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Design Verification 0: ADD4 1: AND5 2: INC 3: JMP 0 4: 27H 5: 39H

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Relatively Simple CPU 64K x 8 memory64K x 8 memory –Address pins A[15..0] –Data Pins D[7..0] 8-bit Accumulator AC8-bit Accumulator AC 8-bit General Purpose Register R8-bit General Purpose Register R 1-bit Flag Register Z1-bit Flag Register Z

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Set

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Non-ISA Registers 16-bit Address Register AR16-bit Address Register AR 16-bit Program Counter PC16-bit Program Counter PC 8-bit Data Register DR8-bit Data Register DR 8-bit Instruction Register IR8-bit Instruction Register IR 8-bit Temporary Register TR8-bit Temporary Register TR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch Cycle FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1 FETCH3: IR  DR, AR  PC

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch and Decode Cycles

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 NOP Execute Cycle NOP1: (no operation)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1 LDAC3: AR  DR,TR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1 LDAC3: AR  DR,TR LDAC4: DR  M

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1 LDAC3: AR  DR,TR LDAC4: DR  M LDAC5: AC  DR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 STAC Execute Cycle STAC1: DR  M, PC  PC + 1, AR  AR + 1 STAC2: TR  DR, DR  M, PC  PC + 1 STAC3: AR  DR,TR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 STAC Execute Cycle STAC1: DR  M, PC  PC + 1, AR  AR + 1 STAC2: TR  DR, DR  M, PC  PC + 1 STAC3: AR  DR,TR STAC4: DR  AC

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 STAC Execute Cycle STAC1: DR  M, PC  PC + 1, AR  AR + 1 STAC2: TR  DR, DR  M, PC  PC + 1 STAC3: AR  DR,TR STAC4: DR  AC STAC5: M  DR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 MVAC and MOVR Execute Cycles MVAC1: R  AC

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 MVAC and MOVR Execute Cycles MVAC1: R  AC MOVR1: AC  R

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JUMP Execute Cycle JUMP1: DR  M, AR  AR + 1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JUMP Execute Cycle JUMP1: DR  M, AR  AR + 1 JUMP2: TR  DR, DR  M

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JUMP Execute Cycle JUMP1: DR  M, AR  AR + 1 JUMP2: TR  DR, DR  M JUMP3: PC  DR,TR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JMPZ Execute Cycles JMPZY: Jump is takenJMPZY: Jump is taken

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JMPZ Execute Cycles JMPZY: Jump is takenJMPZY: Jump is taken JMPZY1: DR  M, AR  AR + 1 JMPZY2: TR  DR, DR  M JMPZY3: PC  DR,TR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JMPZ Execute Cycles JMPZY: Jump is takenJMPZY: Jump is taken JMPZY1: DR  M, AR  AR + 1 JMPZY2: TR  DR, DR  M JMPZY3: PC  DR,TR JMPZN: Jump is not takenJMPZN: Jump is not taken

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JMPZY: Jump is takenJMPZY: Jump is taken JMPZY1: DR  M, AR  AR + 1 JMPZY2: TR  DR, DR  M JMPZY3: PC  DR,TR JMPZN: Jump is not takenJMPZN: Jump is not taken JMPZN1: PC  PC + 1 JMPZN2: PC  PC + 1 JMPZ Execute Cycles

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JPNZ Execute Cycles JPNZY: Jump is takenJPNZY: Jump is taken

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JPNZ Execute Cycles JPNZY: Jump is takenJPNZY: Jump is taken JPNZY1: DR  M, AR  AR + 1 JPNZY2: TR  DR, DR  M JPNZY3: PC  DR,TR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JPNZ Execute Cycles JPNZY: Jump is takenJPNZY: Jump is taken JPNZY1: DR  M, AR  AR + 1 JPNZY2: TR  DR, DR  M JPNZY3: PC  DR,TR JPNZN: Jump is not takenJPNZN: Jump is not taken

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JPNZ Execute Cycles JPNZY: Jump is takenJPNZY: Jump is taken JPNZY1: DR  M, AR  AR + 1 JPNZY2: TR  DR, DR  M JPNZY3: PC  DR,TR JPNZN: Jump is not takenJPNZN: Jump is not taken JPNZN1: PC  PC + 1 JPNZN2: PC  PC + 1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions ADD1: AC  AC + R, IF (AC + R = 0) THEN Z  1 ELSE Z  0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions ADD1: AC  AC + R, IF (AC + R = 0) THEN Z  1 ELSE Z  0 SUB1: AC  AC - R, IF (AC - R = 0) THEN Z  1 ELSE Z  0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions ADD1: AC  AC + R, IF (AC + R = 0) THEN Z  1 ELSE Z  0 SUB1: AC  AC - R, IF (AC - R = 0) THEN Z  1 ELSE Z  0 INAC1: AC  AC + 1, IF (AC + 1 = 0) THEN Z  1 ELSE Z  0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions ADD1: AC  AC + R, IF (AC + R = 0) THEN Z  1 ELSE Z  0 SUB1: AC  AC - R, IF (AC - R = 0) THEN Z  1 ELSE Z  0 INAC1: AC  AC + 1, IF (AC + 1 = 0) THEN Z  1 ELSE Z  0 CLAC1: AC  0, Z  1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions AND1: AC  AC ^ R, IF (AC ^ R = 0) THEN Z  1 ELSE Z  0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions AND1: AC  AC ^ R, IF (AC ^ R = 0) THEN Z  1 ELSE Z  0 OR1: AC  AC  R, IF (AC  R = 0) THEN Z  1 ELSE Z  0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions AND1: AC  AC ^ R, IF (AC ^ R = 0) THEN Z  1 ELSE Z  0 OR1: AC  AC  R, IF (AC  R = 0) THEN Z  1 ELSE Z  0 XOR1: AC  AC  R, IF (AC  R = 0) THEN Z  1 ELSE Z  0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions AND1: AC  AC ^ R, IF (AC ^ R = 0) THEN Z  1 ELSE Z  0 OR1: AC  AC  R, IF (AC  R = 0) THEN Z  1 ELSE Z  0 XOR1: AC  AC  R, IF (AC  R = 0) THEN Z  1 ELSE Z  0 NOT1: AC  AC, IF (AC = 0) THEN Z  1 ELSE Z  0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Establishing Data Paths

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Operations Determine functions of each component AR and PC load and increment dataAR and PC load and increment data DR, IR, R, and TR only load dataDR, IR, R, and TR only load data AC and Z will only load dataAC and Z will only load data

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Preliminary Register Section

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR and IR do not send data to register busAR and IR do not send data to register bus

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR and IR do not send data to register busAR and IR do not send data to register bus Pins D[7..0] are bidirectionalPins D[7..0] are bidirectional

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR and IR do not send data to register busAR and IR do not send data to register bus Pins D[7..0] are bidirectionalPins D[7..0] are bidirectional Bus is 16-bits wide, but some registers have fewer bitsBus is 16-bits wide, but some registers have fewer bits

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR and IR do not send data to register busAR and IR do not send data to register bus Pins D[7..0] are bidirectionalPins D[7..0] are bidirectional Bus is 16-bits wide, but some registers have fewer bitsBus is 16-bits wide, but some registers have fewer bits Register Z is not connected to anythingRegister Z is not connected to anything

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Bidirectional Data Pins

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Final Register Section

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 ALU Design LDAC5: AC  0 + BUS + 0 MOVR1: AC  0 + BUS + 0 ADD1: AC  AC + BUS + 0 SUB1: AC  AC + BUS’ + 1 INAC1: AC  AC CLAC1: AC 

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 ALU Design

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generic Hardwired Control Unit

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generating States FETCH1 = T0 FETCH2 = T1 FETCH3 = T2 NOP11 = INOP ^ T3 LDAC1 = ILDAC ^ T3 LDAC2 = ILDAC ^ T4

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Counter Control Signals INC = 1 when progressing through sequential statesINC = 1 when progressing through sequential states CLR = 1 when returning to FETCH1CLR = 1 when returning to FETCH1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 INCLUDE JAVA APPLET ANIMATION HERE

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Simple CPUs’ Shortcomings More internal registers and cacheMore internal registers and cache Multiple busesMultiple buses Instruction PipelineInstruction Pipeline Larger Instruction SetLarger Instruction Set

Images courtesy of Addison Wesley Longman, Inc. Copyright © Microprocessor Internal Organization

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary CPU SpecificationCPU Specification Very Simple CPUVery Simple CPU Relatively Simple CPURelatively Simple CPU Simple CPU ShortcomingsSimple CPU Shortcomings 8085 Microprocessor8085 Microprocessor