ECE 3561 - Lecture 1 1 ECE 3561 Advanced Digital Design Department of Electrical and Computer Engineering The Ohio State University.

Slides:



Advertisements
Similar presentations
Microcomputer Circuits Prof Jess UEAB 2007 Designing a Microprocessor Chapter 1.
Advertisements

Sistemas Digitais I LESI - 2º ano Lesson 1 - Introduction U NIVERSIDADE DO M INHO E SCOLA DE E NGENHARIA Prof. João Miguel Fernandes
Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering.
ENEL111 Digital Electronics
Register Transfer Level
Give qualifications of instructors: DAP
Electrical and Computer Engineering MIDI Note Number Display UGA Presentation and Demo ECE 353 Lab B.
EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.
Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 1: Introduction Spring 2009 W. Rhett Davis.
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 1 Ch3. Combinatorial Logic Design Modern digital design involves a number of techniques and tools essential.
Hardware Description Languages Drawing of circuit schematics is not practical for circuits containing more than few tens of gates. We need a way to just.
ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.
1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
5.1 Documentation Standards
LabVIEW Design of Digital Integrated Circuits FPGA IC Implantation.
DIGITAL ELECTRONICS CIRCUIT P.K.NAYAK P.K.NAYAK ASST. PROFESSOR SYNERGY INSTITUTE OF ENGINEERING & TECHNOLOGY.
(1) Introduction © Sudhakar Yalamanchili, Georgia Institute of Technology, 2006.
ELEC516/10 course_des 1 ELEC516 VLSI System Design and Design Automation Spring 2010 Course Description Chi-ying Tsui Department of Electrical and Electronic.
Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.
CSET 4650 Field Programmable Logic Devices
Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 1 Digital Systems Design Shyue-Kung Lu Department of Electronic.
Introduction to FPGA AVI SINGH. Prerequisites Digital Circuit Design - Logic Gates, FlipFlops, Counters, Mux-Demux Familiarity with a procedural programming.
Introduction to Digital Design
Shashi Kumar 1 Logic Synthesis: Course Introduction Shashi Kumar Embedded System Group Department of Electronics and Computer Engineering Jönköping Univ.
ECE Lecture 1 1 Introduction to Microcontrolllers Department of Electrical and Computer Engineering The Ohio State University ECE 2560.
Slide No. 1 Course: Logic Design Dr. Ali Elkateeb Topic: Introduction Course Number: COMP 1213 Course Title: Logic Design Instructor: Dr. Ali Elkateeb.
TO THE COURSE ON DIGITAL DESIGN FOR INSTRUMENTATION TO THE COURSE ON DIGITAL DESIGN FOR INSTRUMENTATION.
Welcome to the Department of Engineering Contact us: (207)
Lecture 2 1 ECE 412: Microcomputer Laboratory Lecture 2: Design Methodologies.
COE 405 Design and Modeling of Digital Systems
Galen SasakiEE 260 University of Hawaii1 Electronic Design Automation (EDA) EE 260 University of Hawaii.
1 Combinational Logic Design Digital Computer Logic Kashif Bashir
ELEC692/04 course_des 1 ELEC 692 Special Topic VLSI Signal Processing Architecture Fall 2004 Chi-ying Tsui Department of Electrical and Electronic Engineering.
Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.
Introduction to FPGA Created & Presented By Ali Masoudi For Advanced Digital Communication Lab (ADC-Lab) At Isfahan University Of technology (IUT) Department.
Introduction to Chapter 3  Now that we understand the concept of binary numbers, we will study ways of describing how systems using binary logic levels.
Chapter 0 deSiGn conCepTs EKT 221 / 4 DIGITAL ELECTRONICS II.
ECE 3110: Introduction to Digital Systems Introduction (Contd.)
ECE 3110: Introduction to Digital Systems Introduction (Contd.)
Module 1.2 Introduction to Verilog
Spring 2007 W. Rhett Davis with minor editing by J. Dean Brock UNCA ECE Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 1: Introduction.
VLSI stands for Very-large-scale integration (VLSI) is the process of creating integrated circuit by combining thousands of transistor into a single chip.
Anurag Dwivedi. Basic Block - Gates Gates -> Flip Flops.
Electrical and Computer Engineering University of Cyprus LAB 1: VHDL.
ELEE 4303 Digital II Introduction to Verilog. ELEE 4303 Digital II Learning Objectives Get familiar with background of HDLs Basic concepts of Verilog.
CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson.
Lecture 1 – Overview (rSp06) ©2008 Joanne DeGroat, ECE, OSU -1- Functional Verification of Hardware Designs EE764 – Functional Verification of Hardware.
ECE 551: Digital System Design & Synthesis Motivation and Introduction Lectures Set 1 (3 Lectures)
ECE Lecture 1 1 ECE 561 Digital Circuit Design Department of Electrical and Computer Engineering The Ohio State University.
1 Multiplexers (Data Selectors) A multiplexer (MUX) is a device that allows several low-speed signals to be sent over one high-speed output line. “Select.
Teaching Digital Logic courses with Altera Technology
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
ECE 3110: Introduction to Digital Systems Introduction (Contd.)
Circuit Analyze  Combinational or Sequential logic schematics show the circuit’s hardware implementation and give us some knowledge about the functions.
VHDL From Ch. 5 Hardware Description Languages. History 1980’s Schematics 1990’s Hardware Description Languages –Increased due to the use of Programming.
Lecture 1 – Overview (rSp06) ©2008 Joanne DeGroat, ECE, OSU -1- Functional Verification of Hardware Designs EE764 – Functional Verification of Hardware.
Common Elements in Sequential Design. Lecture 3 topics  Registers and Register Transfer  Shift Registers  Counters Basic Counter Partial sequence counters.
1 Digital Logic Design (41-135) Introduction Younglok Kim Dept. of Electrical Engineering Sogang University Spring 2006.
Design and Documentation
Combinational Logic Design
Overview Part 1 – Design Procedure Beginning Hierarchical Design
Digital Design.
Programmable Logic Devices: CPLDs and FPGAs with VHDL Design
Schematics 201 Lecture Topic: Electrical Symbols
Lecture 1.3 Hardware Description Languages (HDLs)
Lesson 4 Synchronous Design Architectures: Data Path and High-level Synthesis (part two) Sept EE37E Adv. Digital Electronics.
ECNG 1014: Digital Electronics Lecture 1: Course Overview
L25 – Final Review AU 15 Final Exam – Classroom – Journalism 300
Logic Gates By: Asst Lec. Besma Nazar Nadhem
Presentation transcript:

ECE Lecture 1 1 ECE 3561 Advanced Digital Design Department of Electrical and Computer Engineering The Ohio State University

ECE Lecture 1 2 Today Syllabus The Course Intro Syllabus detail discussion

ECE Lecture 1 3 Course Philosophy and Objective Familiarize students with advanced digital design principles and practice Learn to use actual chips for designing practical digital circuits Learn modern design technologies with Quartus software and programmable chips See the role HDLs have played in design methodology

ECE Lecture 1 4 Modern Digital Design Real logic designs are too large to solve by straight theoretical approach Today’s methodology Requires use of subdivision of system into Logic Building Blocks. Far above the gate level of AND/OR gates but far below the processor level. Use of CAD Use of PLDs and FPGA – state of the art programmable chips.

ECE Lecture 1 5 Course Topics Review of combination and sequential logic Analysis of sequential circuits Logic Building Blocks and applications Counters, shift registers, comparators Review of traditional approaches to sequential design FPGAs and CPLDs

ECE Lecture 1 6 Course Topics (2) Structured Sequential Design Based on Logical Building Blocks (LBBs) Complex System = Sum of smaller systems Organize functions, inputs, outputs from word description of problem Art (creative process) – choose LBBs and organize Science – function and timing Design Technology Using modern CAD Use programmable chips – PLDs and FPGAs Use of HDLs – VHDL, Verilog, System Verilog, System C

ECE Lecture 1 7 Combination Logic Design In today’s world digital circuits, both combinational and sequential, have millions of gates and several hundred, if not thousands, of inputs and outputs. How do you handle this? Challenges the scope of human comprehension. How much information can a human comprehend?

ECE Lecture 1 8 Documentation “Good documentation is essential for correct design” (from text) Design specification must be accurate, complete and understandable The starting place is a good specification of the circuit or system.

ECE Lecture 1 9 The Specificaiton Describes exactly what the circuit of system is supposed to do. All inputs and outputs are accurately specified. The internal function performed is fully specified. Algorithm implements is documented Data format and transformations are specified Timing is clear and precise

ECE Lecture 1 10 Other aspects of documention Block Diagram Schematic Diagram Timing Diagram Structured Logic Description HDL description both documents and allows for simulation and synthesis of the design Circuit Description

ECE Lecture 1 11 Block Diagrams Shows inputs and outputs and functional modules

ECE Lecture 1 12 Gate Symbols

ECE Lecture 1 13 Active high and Active low

ECE Lecture 1 14 Circuit Timing “Timing is everything” In Comedy In Investing In digital design When the inputs change the output of the gate will respond to that change. The output will change (if it does) after the internal circuitry of the gate settles to the new output state.

ECE Lecture 1 15 Circuit Timing (2) Glitches on the output occur when the inputs do not arrive simultaneously. It is almost impossible to design a combinational logic circuit that is 100% glitch free. It is possible to create a design in which the glitches that do occur are insignificant. This is why synchronous systems have a minimum clock period.

ECE Lecture 1 16 Timing Analysis Tools Circuit timing waveforms

Expansion into this offering This slide will explain the specifics of how each objective will be achieved. Slide 5 – Logic building blocks The datapath of a simple microcontroller will be implemented by creating small components from gates and then integrating them together. Sequential circuits The controller for the simple microcontroller will be implemented, illustrating the complexity of controllers of modern processors. ECE Lecture 1 17

ECE Lecture 1 18 Assignment None today – Read in text Assignments will be due 2 classes after assigned to the drop box on Carmen. No paper submissions – all are electronic.