Gate-Level Minimization1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN
Gate-Level Minimization2 What is minimization? Simplifying boolean expressions Algebraic manipulations is hard since there is not a uniform way of doing it Karnaugh map or K-map techniques is very commonly used
Gate-Level Minimization3 Two-Variable K-Map
Gate-Level Minimization4 Example
5 ExampleExample
6 Three-Variable K-Map
Gate-Level Minimization7 Three-Variable K-Map
Gate-Level Minimization8 Example
9 Note In K-maps, you can have groups of 2, 4, 8, or 16 You cannot have groups of other combinations such as a group of 6
Gate-Level Minimization10 Exercises
Gate-Level Minimization11 Example Represent F in the minimal format and draw the network diagram
Gate-Level Minimization12 Example Represent F in the minimal format and draw the network diagram
Gate-Level Minimization13 Example Represent F in the minimal format and draw the network diagram
Gate-Level Minimization14 Four-Variable K-Map
Gate-Level Minimization15 Four-Variable K-Map
Gate-Level Minimization16 Example Represent F in the minimal format and draw the network diagram
Gate-Level Minimization17 Example Represent F in the minimal format and draw the network diagram
Gate-Level Minimization18 Example Represent F in the minimal format and draw the network diagram
Gate-Level Minimization19 Prime Implicants You must cover all of the minterms You must avoid redundancy You must follow some rules Prime Implicant A product term that is generated by combining the maximum number of adjacent squares in the map Essential Prime Implicant A minterm that is covered by only one prime implicant
Gate-Level Minimization20 Maxterm Simplification Remember
Gate-Level Minimization21 Example Simplify F in product of sums
Gate-Level Minimization22 Example (cont) Step – 1 Fill the K-map for F
Gate-Level Minimization23 Example (cont) Step – 1 Fill the K-map for F
Gate-Level Minimization24 Example (cont) Step – 2 Fill zeros in the rest of the squares
Gate-Level Minimization25 Example (cont) Step – 3 Cover zeros. This is your F’
Gate-Level Minimization26 Important
Gate-Level Minimization27 Don’t Care Conditions A network is usually composed of sub- networks Net-1 may not produce all combinations of A,B, and C In this case, F don’t care about those combinations ABCABC F Net-1Net-2
Gate-Level Minimization28 Don’t Care Conditions x x 1 1 X can be considered as 0 or 1, whichever is more convenient
Gate-Level Minimization29 NAND/NOR Implementations AND, OR, and NOT gates can be used to construct the digital systems However, it is easier to fabricate NAND and NOR gates So try to replace AND, OR, and NOT gates with NAND or NOR gates
Gate-Level Minimization30 NAND Implementation First implement with AND-OR Put bubble at the output of each AND gate Put bubbles at the inputs of each OR gate Place necessary inverters
Gate-Level Minimization31 Example
Gate-Level Minimization32 Example
Gate-Level Minimization33 Example
Gate-Level Minimization34 NOR Implementation First implement with AND-OR Put bubble at the inputs of each AND gate Put bubbles at the output of each OR gate Place necessary inverters
Gate-Level Minimization35 Example
Gate-Level Minimization36 Study Problems Course Book Chapter – 3 Problems 3– 1 3 – 3 3 – 5 3 – 7 3 – 12 3 – 15 3 – 18
Gate-Level Minimization37 Questions