ECE 753: FAULT-TOLERANT COMPUTING Kewal K.Saluja Department of Electrical and Computer Engineering Test Generation and Fault Simulation Lectures Set 3

ECE 753 Fault Tolerant Computing2 Overview Introduction Basics of testing Complexity reduction –test generation complexitytest generation complexity –reduction of fault listreduction of fault list Fault Simulation Test generation –combinational circuitscombinational circuits –sequential circuitssequential circuits –design for testabilitydesign for testability –built-in self-testbuilt-in self-test

ECE 753 Fault Tolerant Computing3 Recap Think about PROJECT Fault models –HW and SWHW and SW –Error modelsError models –System level modelsSystem level models

ECE 753 Fault Tolerant Computing4 Introduction References What is testing? How is it done? Why test? What to test for? - fault model Justification of the model Relation between testing and fault- toleranceRelation between testing and fault- tolerance

ECE 753 Fault Tolerant Computing5 Introduction (contd.) References [goel:81] P. Goel, An implicit enumeration algorithm to generate tests for combinational circuits, IEEE TC, March 1981[goel:81] P. Goel, An implicit enumeration algorithm to generate tests for combinational circuits, IEEE TC, March 1981 Many books and papers in the area of testing digital circuitsMany books and papers in the area of testing digital circuits Text does not deal with testing issues Book by Johnson [john:89] contains a simple and necessary material for this courseBook by Johnson [john:89] contains a simple and necessary material for this course Book by Siewiorek and Swartz [siew:99] discusses some of the classical methodsBook by Siewiorek and Swartz [siew:99] discusses some of the classical methods

ECE 753 Fault Tolerant Computing6 Introduction (contd.) What is testing? A method of determining if a given product/device is “good” or “faulty”A method of determining if a given product/device is “good” or “faulty” Normally a Go/NoGo approach - “detection” Occasionally determine the location of fault site - “diagnosis”Occasionally determine the location of fault site - “diagnosis” apply input - observe outputs to device under test (DUT) - many other acronyms such as CUT, PUT, BUT,...device under test (DUT) - many other acronyms such as CUT, PUT, BUT,...

ECE 753 Fault Tolerant Computing7 Introduction (contd.) What is testing? Typical constraints no internal probing of the device internal details may or may not be available - hence may have to take a black box approach to testinginternal details may or may not be available - hence may have to take a black box approach to testing How is it done? Tester based –gold unitgold unit –simulationsimulation Non-tester based –self-testself-test

ECE 753 Fault Tolerant Computing8 Introduction (contd.) Why Test? Determine if a product is good or faulty Business/cost - cost of not testing is too high rule of 10 quality - closely related to testing

ECE 753 Fault Tolerant Computing9 Introduction (contd.) What to test for? - Fault model Assumptions digital circuit gate level description available apply input and observe output - no internal probing or any other measurementsapply input and observe output - no internal probing or any other measurements logic testing - observe logic level Which fault model to chose? Single stuck-at fault model

ECE 753 Fault Tolerant Computing10 Introduction (contd.) Justification of the model Empirical evidence - it works Simple and practical tractable easy to use - many existing hardware and software tools use this modeleasy to use - many existing hardware and software tools use this model It has stood the test of time

ECE 753 Fault Tolerant Computing11 Introduction (contd.) Relation between testing and fault- toleranceRelation between testing and fault- tolerance Follows from the definitions of reliability and availability - conditions at t = 0Follows from the definitions of reliability and availability - conditions at t = 0 It is the basic method of “fault avoidance” for fault-toleranceIt is the basic method of “fault avoidance” for fault-tolerance

ECE 753 Fault Tolerant Computing12 Basics of testing Truth table approach How to reduce number of tests Quality of tests

ECE 753 Fault Tolerant Computing13 Basics of testing (contd.) Truth table approach An example Limitations large number of inputs large number of faults large number of tests difficulty in handling sequential circuits

ECE 753 Fault Tolerant Computing14 Basics of testing (contd.) How to reduce number of tests An example Methods sequential approach find a test for the fault not yet detected determine all faults detected by it - fault simulation do not generate tests for the faults so detected cover table approach ability to provide an optimal solution (test set containing fewest number of tests)ability to provide an optimal solution (test set containing fewest number of tests)

ECE 753 Fault Tolerant Computing15 Basics of testing (contd.) Quality of tests Intuitive figure of merit more fault a test set detects, the better the test set is Fault coverage ratios of faults detected by a test set to the total number of possible faults in the circuitratios of faults detected by a test set to the total number of possible faults in the circuit Methods to obtain coverage metric create fault list simulate circuit with and without fault and determine detected faultssimulate circuit with and without fault and determine detected faults obtain fault coverage

ECE 753 Fault Tolerant Computing16 Complexity reduction Test generation complexity –equivalent to satisfiability problemequivalent to satisfiability problem –an NP complete problem for combinational circuitsan NP complete problem for combinational circuits –clearly NP for sequential circuitsclearly NP for sequential circuits

ECE 753 Fault Tolerant Computing17 Complexity reduction Fault list reduction –fault equivalence of stuck-at faultsfault equivalence of stuck-at faults Two faults are said to be equivalent if the circuit behavior in the presence of either of these two faults is identicalTwo faults are said to be equivalent if the circuit behavior in the presence of either of these two faults is identical –example to show fault equivalenceexample to show fault equivalence –methods to identify fault equivalence and their application to reduce fault listmethods to identify fault equivalence and their application to reduce fault list

ECE 753 Fault Tolerant Computing18 Complexity reduction (contd.) Modeling other faults using stuck-at fault modelModeling other faults using stuck-at fault model –example - stuck-on faultexample - stuck-on fault –multiple faults using a single fault modelmultiple faults using a single fault model using extra inputs and logic using extra logic only

ECE 753 Fault Tolerant Computing19 Simulation and fault simulation –2 value simulation2 value simulation –3 value simulation3 value simulation –more values (5 and 9)more values (5 and 9) –symbolic simulationsymbolic simulation

ECE 753 Fault Tolerant Computing20 Test generation Combinational circuit test generation –random pattern test generationrandom pattern test generation algorithm –generate a random inputgenerate a random input –simulate and determine new faults detectedsimulate and determine new faults detected –continue till desired stopping condition is metcontinue till desired stopping condition is met advantages and issues –simplesimple –when to quit?when to quit? –how does it perform?how does it perform?

ECE 753 Fault Tolerant Computing21 Test generation (contd.) Combinational circuit test generation –PODEMPODEM basics of test generation –fault excitationfault excitation –fault propagationfault propagation D notation –explain 5-value logic - 0, 1, x, D, U (D_bar)explain 5-value logic - 0, 1, x, D, U (D_bar)

ECE 753 Fault Tolerant Computing22 Test generation (contd.) Combinational circuit test generation –PODEM (contd.)PODEM (contd.) algorithm sketch - informal –excite faultexcite fault »choose an unassigned inputchoose an unassigned input »place it on decision treeplace it on decision tree »assign a value to the input and check fault site is D, U, X, or a constant.assign a value to the input and check fault site is D, U, X, or a constant. D or U - excited X - not yet excited constant - same as fault value - BACKTRACK constant - same as fault value - BACKTRACK

ECE 753 Fault Tolerant Computing23 Test generation (contd.) Combinational circuit test generation –PODEM (contd.)PODEM (contd.) –propagate faultpropagate fault »choose an unassigned inputchoose an unassigned input »place it on decision treeplace it on decision tree »assign a value to the input and check if still D or U in the circuit and if propagatedassign a value to the input and check if still D or U in the circuit and if propagated if no D or U in the circuit D-frontier (intutively speaking - no gate with an input of D or U and output of X) then backtrack if no D or U in the circuit D-frontier (intutively speaking - no gate with an input of D or U and output of X) then backtrack

ECE 753 Fault Tolerant Computing24 Test generation (contd.) Combinational circuit test generation –PODEM (contd.)PODEM (contd.) –flow chart from the paperflow chart from the paper –an example circuit for test generation to explain the conceptsan example circuit for test generation to explain the concepts »back coneback cone »backtrace - different from backtrackbacktrace - different from backtrack »backtracing for desired effects at the correct locationbacktracing for desired effects at the correct location »backtracing for desired valuebacktracing for desired value »backtracing using easy/hard heuristicbacktracing using easy/hard heuristic

ECE 753 Fault Tolerant Computing25 Test generation (contd.) Combinational circuit test generation –PODEM (contd.)PODEM (contd.) we have a test –can it detect more faults?can it detect more faults? »Fault simulateFault simulate »fill x’s to detect even more faultsfill x’s to detect even more faults random fill deterministic fill –fault droppingfault dropping

ECE 753 Fault Tolerant Computing26 Test generation (contd.) Sequential circuit test generation –checking sequence approachchecking sequence approach assume knowledge of state description –structural approach - gate level descriptionstructural approach - gate level description random testing –try random inputtry random input –fault simulatefault simulate –compute fault coveragecompute fault coverage –NOT VERY EFFECTIVE GENERALLYNOT VERY EFFECTIVE GENERALLY

ECE 753 Fault Tolerant Computing27 Test generation (contd.) Sequential circuit test generation –structural approach - (contd.)structural approach - (contd.) sequential test generation –time frame expansion modeltime frame expansion model –example of a circuitexample of a circuit –generate a test using combinational methodgenerate a test using combinational method –convert the combinational test to a test seequenceconvert the combinational test to a test seequence

ECE 753 Fault Tolerant Computing28 Test generation (contd.) Design for testabilitiy –model of sequential circuitmodel of sequential circuit –convert the memory elements to a string of connected elements - shift registerconvert the memory elements to a string of connected elements - shift register –generate test for combinational circuitgenerate test for combinational circuit –test application consists oftest application consists of scan-in apply system clock (apply test and capture responses) scan-out –overlapping of scan-in and scan-outoverlapping of scan-in and scan-out

ECE 753 Fault Tolerant Computing29 Test generation (contd.) Built-in self-test –concept of Linear Feedback Shift Register (LFSR)concept of Linear Feedback Shift Register (LFSR) a random pattern generator a signature analyser –model a sequential circuit as combinational circuit with inputs and outputsmodel a sequential circuit as combinational circuit with inputs and outputs –convert the input memory elements as a random pattern generator LFSRconvert the input memory elements as a random pattern generator LFSR –convert the output memory elements to a signature analyzerconvert the output memory elements to a signature analyzer

ECE 753 Fault Tolerant Computing30 Summary Basics of testing Fault list reduction Fault simulation –fault coverage computationfault coverage computation Test Generation –combinational circuits - PODEMcombinational circuits - PODEM –sequential circuits - time frame expansionsequential circuits - time frame expansion –DFT - full scan approachDFT - full scan approach –BIST - key element LFSRBIST - key element LFSR