Review of Devices; cnt’d ECE 6466 “IC Engineering” Dr. Wanda Wosik Chapter 1 Review of Devices; cnt’d : Silicon VLSI Technology Fundamentals, Practice and Modeling by J. D. Plummer, M. D. Deal, and P. B. Griffin UH; F2014

Review: materials and devices (after Streetman & Kano) Semiconductors: Si, Ge, and Compound (III-V, II-VI) Four valence electrons Covalent bonding: no free electrons at 0K N-type dopants P-type dopants Dopants have to be compatible with processing (ex. slow diffusion through oxide) to have high solubility in Si

Intrinsic Semiconductor Electron and hole generation occur at elevated temperature (above 0K). n=p Energy Band Gap determines the intrinsic carrier concentration. ni EgGe< EgSi< EgGaAs For devices we need concentrations: n and p>>ni

N- and p-type semiconductor n≈ND p≈NA Ingot crystal Possible dopant deactivation & defect formation

Resistivity as a Function of Dopant Concentration r=1/(qµnn+qµpp) µ carrier mobility depends on scattering i.e. dopants, lattice imperfections (defects) and vibration (temperature) µn>µp

Electrical Properties of Semicondutors Explained by a Band Model and Bond Model Intrinsic (Undoped) Silicon T>0K Energy Gap n=p=ni n=p

Electrical Properties of Semicondutors Explained by a Band Model and Bond Model n-type Silicon doped with As n=NAs Very small ionization energies ED and EA moves

Dopant Ionization n-type semiconductor nn>>pn ni≈pi intrinsic semiconductor ni=1.45x1010cm-3 at RT (300K)

Intrinsic Semiconductor n-type Semiconductor p=type Semiconductor Distribution of Free Carries (electrons and holes) Obeys Pauli Exclusion Principle Fermi Dirac probability function: Fermi level is the energy at which the probability of finding an electron F(E) is 0.5 Intrinsic Semiconductor n-type Semiconductor p=type Semiconductor n=Nd Conduction Band Majority carriers EF ≈Eg/2 below Ei above Ei Majority carriers Valence Band p=Na

Carriers’ Statistics F-D statistics becomes Boltzmann if E-EF>>kT (low doped) Effective density of states NC and NV Pauli exclusion principle important here Energy n=niexp(EF-Ei/kT) Parabolic density of states np=ni2 p=niexp(Ei-EF/kT) Density of states Density of electrons and holes Probability function

Carrier Concentrations EC n= Ncexp[-(EC-EF)/kT]=niexp(EF-Ei/kT) Heavy doping moves EF to EC EF p= Ncexp[-(EF-EV)/kT]= niexp(Ei-EF/kT) EG= EC-EV Band gap EV np=ni2 =NCNVexp(-EG/kT)=KT3exp(- EG/kT) For small dopant concentrations or close to the intrinsic conditions (ex. at processing temperatures) charge neutrality should be used: ND++p=NA-+n then n=1/2[N+D- N-A)+√(N+D - N-A)2+4ni2] p=1/2[N-A -N+D)+√(N-A - N+D)2+4ni2]

Energy Band Dependence on Temperature EG shrinks with T Energy Band Dependence on Temperature Larger temperature weakens the bonding between atoms causing the band gap energy EG (energy needed to free e-h pairs) to decrease EF EG(eV)=1.17-4 -4. 73x10-4T2/(T+636) ≈1.16 - (3x10-4)T

Example: doping by As and B results in p-type Si at RT Energy levels for shallow dopants are close to the majority carrier bands RT 1000°C and in intrinsic Si at 1000°C n≈p≈ni at 1000°C p>>n

Recombination of Carriers Si is an indirect semiconductor so indirect recombination (Shockley-Read-Hall) occurs through traps located in the mid-gap n-type Si; a trap (below EF) is always filled with electron=majority carrier and waits for a minority hole. intrinsic Si tR=1/svthNt lifetime capture cross section thermal velocity, and traps

Carier Recombination and Generation Traps (defects,metal impurities) present in silicon act either to annihilate carriers (recombination) or produce (generation) them. SRH recombination/generation rate np>ni2 U>0 recombination np<ni2 U<0 generation lifetime tr≠tg Umax for ET=Ei Surface of Si with traps lead to the surface recombination velocity, which affects carrier lifetime s=svthNit

Semiconductor Devices p-n Diodes n+ for low resistance Reverse biased diode Forward biased diode after Kano, Sem. Dev.

p-n Diodes at Thermal Equilibrium Dopants’ positions are fixed Majority holes Majority electrons Minority electrons Minority holes Carriers move and create depletion layers after Kano, Sem. Dev.

p-n Diodes at Thermal Equilibrium At thermal equilibrium charge neutrality qN+dxn=qN-Axp leads to asymmetrical depletion layers Electric field only in the depletion layer Uncompensated acceptors and donors

p-n Diodes at Thermal Equilibrium Build-in voltage determined by doping on both sides of the p-n junction n0n≈ND p0n≈ni2/ND No current flows at thermal equilibrium after Kano, Sem. Dev.

p-n Diodes Under Bias Reverse biased diode (- +) Forward biased diode Minority electrons and holes drift (small current) Majority electrons (and holes) diffuse, become minority carriers and produce large current Forward biased diode I (+ -) I~exp(qV/kT) holes V after Kano, Sem. Dev.

p-n Diodes Under Forward Bias Depletion layer shrinks Electric field decreases Junction potential decreases by Va J  Energy barrier decreases by qVa J~exp(qVa/kT) after Kano, Sem. Dev.

p-n Diodes Under Reverse Bias Depletion layer spreads mainly to the low doped side Electric field increases Junction potential increases by Va Energy barrier increases by qVa J0A after Kano, Sem. Dev.

Junction at Thermal Equilibrium Minority and majority carriers Boltzman approximation Built-in voltage E-field is where Ei=f(x) Fermi potentials in n and p-regions Electrostatic potential Poisson’s equation:

Injection and Extraction p-n Diodes Under Bias Carrier Injection and Extraction No recombination assumed in the SCR Current distribution in a p-n diode For the forward biasing condition after Neudeck

Breakdown of a p-n Diode Zener effect Avalanche effect after Kano and Streetman

Breakdown Voltage of a p-n Diode Eg  5-7V Ebr field increases with ND but not very much Wdepl~1/√ND Vbr=Ebr•Wdepl so Vbr decreases with ND after Kano and Streetman

Transistors for Digital and Analog Applications MOSFET and Bipolar Junction Transistors

Bipolar Transistors VBE>0 VBC<0 a<1 E-B junction is forward biased=injects minority carriers to the base Base (electrically neutral) is responsible for electron transport via diffusion (or drift also if the build in electric field exists) to collector C-B diode is reverse biased and collects transported carries VBE>0 VBC<0 IE IC IB a<1 IE=IEn+IEp IC=aIE IB=IEp+Irec

Bipolar Junction Transistors p-n-p Individual device n-p-n Integrated circuit BJT

Bipolar Junction Transistors Forwards bias Reverse bias minority carriers Injected electrons Extracted electrons holes

Bipolar Junction Transistors Currents’ Components small

Forward Operation Mode Bipolar Junction Transistors Early Effect Forward Operation Mode Early Voltage

Bipolar Junction Transistors Breakdown Voltages Common Emitter Common Base Collector-Base junction

Bipolar Junction Transistors Current Gain b =a/1-a b=IC/IB Kirk Effect Recombination in the E-B Space Charge Region Gummel Plot

Bipolar Junction Transistors and a Switch Schottky Diode used in n-p-n BJTs for faster speed

MOS Field Effect Transistors (MOSFET) NMOS and PMOS (used in CMOS circuits) VG>VT to creates strong inversion Oxide depletion

Operation of NMOS-FET Linear Region, Low VD Saturation Region, Channel Starts to Pinch-Off Saturation Region, channel shortens beyond pinch-off, L’<L

Operation of MOS-FET ID(VD) Channel-Length-Modulation (Shorten by Depletion Layer) ID=kp[(VG-VT)VD-VD2/2 Device transconductance kp=µnCoxW/L is larger for NMOS than PMOS In CMOS for compensation of the mobility differences use Wp>Wn

Scaled Down NMOS Drain Induced Barrier Lowering (DIBL) Proximity of the drain depletion layer charge sharing DIBL

Modern MOS Transistors Gate isolation Source Drain LDD LDD used to reduce the electric field in the drain depletion region and hot carrier effects Self aligned contacts decrease the resistance

Semiconductor Technology Families First circuits were based on BJT as a switch because MOS circuits limitations related to large oxide charges isolation BL n-p-n

NMOS and CMOS Technologies Enhancement NMOS Depletion NMOS 1970s 1980s and beyond NMOS PMOS Smaller power consumption

Challenges For The Future Materials/process innovations • Having a “roadmap” suggests that the future is well defined and there are few challenges to making it happen. • The truth is that there are enormous technical hurdles to actually achieving the forecasts of the roadmap. Scaling is no longer enough. • 3 stages for future development: “Technology Performance Boosters” Invention Gate • Spin-based devices • Molecular devices • Rapid single flux quantum • Quantum cellular automata • Resonant tunneling devices • Single electron devices Source Drain ??? Materials/process innovations NOW Beyond Si CMOS IN 15 YEARS?? Device innovations IN 5-15 YEARS Plummer et al.

The traditional finFET (upper left), a trigate on SOI (upper right), trigate on bulk silicon (lower left) and a pseudo-trigate on SOI (lower right). (Source: Texas Instruments)

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Broader Impact of Silicon Technology Tip on Stage Individual Actuator Part of 12 x 12 array Cornell University -0.75V -2.5V -2.25V -2V -1.75V -1.5V -1.25V -1V -0.5V Source Gate Drain SiO2 Stanford, Cornell • Many other applications e.g. MEMs and many new device structures e.g. carbon nanotube devices, all use basic silicon technology for fabrication. Plummer et al.

Summary of Key Ideas • ICs are widely regarded as one of the key components of the information age. • Basic inventions between 1945 and 1970 laid the foundation for today's silicon industry. • For more than 40 years, "Moore's Law" (a doubling of chip complexity every 2-3 years) has held true. • CMOS has become the dominant circuit technology because of its low DC power consumption, high performance and flexible design options. Future projections suggest these trends will continue at least 15 more years. • Silicon technology has become a basic “toolset” for many areas of science and engineering. • Computer simulation tools have been widely used for device, circuit and system design for many years. CAD tools are now being used for technology design. • Chapter 1 also contains some review information on semiconductor materials semiconductor devices. These topics will be useful in later chapters of the text. Plummer et al.